DA9178.001
10 Dec, 2003
SAMPLES IN SBDIL 20 PACKAGE
VDD 1
NC 2
QOP 3
NC 4
QI 5
NC 6
QOM 7
NC 8
AGC 9
NC 10
9178Ax
YYWW
XXXXX.X
20 VSS
19 NC
18 RFM
17 RFP
16 NC
15 PDN
14 AON
13 DEC
12 NC
11 OUT
Top Marking Definitions:
YYWW = Year Week
XXXXX.X = Lot Number
x =1, 5 Sample Version Number
PIN DESCRIPTION
Pin Name
VDD
NC
QOP
NC
QI
NC
QOM
NC
AGC
NC
OUT
NC
DEC
AON
PDN
NC
RFP
RFM
NC
VSS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Type
P
AO
AI
Function
Positive Power Supply
Quartz Filter Output for Crystal
1
Quartz Filter Input for Crystal and
External Compensation Capacitor
1
AO
Quartz Filter Output for External
Compensation Capacitor
AGC Capacitor
Receiver Output
Demodulator Capacitor
AGC On Control
Power Down Input
Positive Receiver Input
Negative Receiver Input
Power Supply Ground
2
Note
AO
DO
AO
DI
AI
AI
AI
G
3
4
Notes:
1) Pins 4 and 6 around quartz crystal filter input pins must be connected to VSS to eliminate DIL package
leadframe parasitic capacitances disturbing the crystal filter performance. All other NC (Not Connected)
pins are also recommended to be connected to VSS to minimize noise coupling.
2) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced
(modulated)
-
the output is a current source/sink with |I
OUT
| > 5
µA
-
at power down the output is pulled to VSS (pull down switch)
3) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (working)
- Internal pull-up with current < 1
µA
which is switched off at power down
4) PDN = VSS means receiver on; PDN = VDD means receiver off
-
Fast start-up is triggered when the receiver is after power down (PDN=VDD) controlled to power up
(PDN=VSS) i.e. at the falling edge of PDN signal.
7 (8)
MAS [ MICRO ANALOG SYSTEMS ]
