DA6512.003
2 December, 2016
RESET REGISTER (E0/60HEX
)
This register is used to reset all control registers
(addresses E1H…EEH) to a zero value. There are
no data bits in this register. However it is necessary
to write dummy data to this register to make a reset.
The reset will take place immediately after any data
has been written to the address E0/60HEX via the
I2C or SPI interface.
TEST REGISTER (E1/61HEX
)
In normal operation the Test register value is 00HEX
and the internal clock oscillator frequency 200 kHz
is used for all the measurements.
The STEST bits are used for connecting different
internal signals to the TEST1 and TEST2 pins. In
STEST=101 test setup TEST1 and TEST2 operate
as positive and negative voltage inputs respectively
which are connected to the differential input of the
ΔΣ-ADC.
FOSC can be used to force the internal oscillator to
be on all the time. This is for internal oscillator
trimming purpose only. Normally (FOSC=0) the
internal oscillator is turned on only during the
measurements to save power and the OSC pin
output is at logic low. To get the internal 200 kHz
clock signal out from OSC pin it is necessary to set
FOSC=1.
By setting the SOSC bit it is possible to optionally
divide the internal system clock frequency by 2, 4 or
8. The undivided 200 kHz system clock frequency
allows measuring capacitances up to around 20pF
but with the maximum division option
8
capacitances up to 160pF. However note that only
sensor base capacitance scales up this much by
clock frequency but the maximum changing
capacitance range is smaller (see ELECTRICAL
CHARACTERISTICS tables).
The SEL_EXTCLK bit selects between internal
clock oscillator (OSC pin as digital output) and
external clock signal (OSC pin as digital input).
External clock selection may come necessary if the
sensor capacitance is too high to be used with the
internal 200 kHz or divided clock frequency options
(see SOSC bits in table 2). The maximum external
clock frequency depends on maximum sensor
capacitance; fEXT=200kHz*20pF/CS_MAX. Note that if
SEL_EXTCLK=1 is selected the internal oscillator is
disabled and OSC pin acts as digital input despite of
FOSC selection.
Note that the frequency division selection SOSC
does not apply to OSC pin clock signals. The
internal 200 kHz clock signal from OSC pin and the
external clock signal applied to OSC pin are not
affected by the SOSC divider options.
Table 2. MAS6512 test register (E1/61HEX) description
Bit
Bit Name
Description
Value
Function
Number
7
6
-
Not used
X
0
1
0
1
-
FOSC
Forces the oscillator on
without conversion
Selects external clock
OSC is on only during conversion
OSC is forced on
5
SEL_EXTCLK
STEST
Internal clock, OSC output (default)
An external clock (OSC input)
can be connected to OSC and the
internal oscillator is disabled
Reserved for internal testing purpose
(TEST1 and TEST2 are outputs)
4-2
TEST1 and TEST2
signal selection
000…100
101
TEST1 and TEST2 as inputs
110…111
No function
1-0
SOSC
Select system clock
frequency
00
01
10
11
f SYS_CLK = 200 kHz
f SYS_CLK = 100 kHz (div by 2)
f SYS_CLK = 50 kHz (div by 4)
f SYS_CLK = 25 kHz (div by 8)
X = Don’t care
11 (32)
MAS [ MICRO ANALOG SYSTEMS ]
