DA6180C.000
26 November, 2010
MAS6180C SAMPLES IN DIL-20 PACKAGE
1
VDD 2
3
QOP 4
QOM 5
6
QI 7
AGC 8
9
OUT 10
MAS6180zz
YYWW
XXXXX.X
20 VSS
19
18 RFIM
17 RFIP
16
15
14 PDN
13 AON
12 DEC
11
Top Marking Definitions:
YYWW = Year Week
XXXXX.X = Lot Number
zz =Sample Version
PIN DESCRIPTION
Pin Name
VDD
QOP
QOM
QI
AGC
OUT
DEC
AON
PDN
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Type
NC
P
NC
AO
AO
NC
AI
AO
NC
DO
NC
AO
DI
DI
NC
NC
AI
AI
NC
G
Function
Positive Power Supply
Positive Quartz Filter Output
Negative Quartz Filter Output
Quartz Filter Input for Crystal
AGC Capacitor
Receiver Output
Demodulator Capacitor
AGC On Control
Power Down Input
3
Note
1
2
4
5
RFIP
RFIM
VSS
Positive Receiver Input
Negative Receiver Input
Power Supply Ground
6
6
A = Analog, D = Digital, P = Power, G = Ground, I = Input, O = Output, NC = Not Connected
Notes:
1) QOM pin is electrically unconnected in MAS6180C1 version
2) Pin 6 between QOM and QI must be connected to VSS to eliminate DIL package lead frame parasitic
capacitances disturbing the crystal filter performance. All other NC (Not Connected) type pins are also
recommended to be connected to VSS to minimize noise coupling.
3) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced (modulated)
-
the output is a current source/sink with |I
OUT
| > 5
µA
-
at power down the output is pulled to VSS (pull down switch)
4) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (working)
-
Internal pull-up with current < 1
µA
which is switched off at power down
5) PDN = VSS means receiver on; PDN = VDD means receiver off
-
Fast start-up is triggered when the receiver is after power down (PDN=VDD) controlled to power up
(PDN=VSS) i.e. at the falling edge of PDN signal.
6) Receiver inputs RFIP and RFIM have both 1.4 MΩ biasing resistors towards VDD
8 (13)
MAS [ MICRO ANALOG SYSTEMS ]
