DA6180B.002
5 May, 2011
PIN CONFIGURATION & TOP MARKING FOR PLASTIC TSSOP-16 PACKAGE
VSS
VDD
QOP
QOM
RFIM
RFIP
QI
AGC
PDN
AON
DEC
Top Marking Definitions:
z = Version Number
YYWW = Year Week
OUT
PIN DESCRIPTION
Pin Name
Pin
Type
Function
Note
VDD
QOP
QOM
1
2
3
P
Positive Power Supply
AO
AO
Positive Quartz Filter Output for Crystal
Negative Quartz Filter Output for
External Compensation Capacitor or
Second Crystal
1
2
4
5
NC
AI
QI
Quartz Filter Input for Crystal and
External Compensation Capacitor
AGC Capacitor
AGC
6
AO
NC
DO
AO
DI
7
OUT
DEC
AON
PDN
8
Receiver Output
3
9
Demodulator Capacitor
AGC On Control
10
11
12
13
14
15
16
4
5
DI
Power Down Input
NC
AI
RFIP
Positive Receiver Input
6
6
NC
AI
RFIM
VSS
Negative Receiver Input
Power Supply Ground
G
A = Analog, D = Digital, P = Power, G = Ground, I = Input, O = Output, NC = Not Connected
Notes:
1) External crystal compensation capacitor pin QOM is connected only in MAS6180B5 version. It is left
unconnected in MAS6180B1 version which has internal compensation capacitor.
2) Pin 4 between QOM and QI must be connected to VSS to eliminate TSSOP package lead frame parasitic
capacitances disturbing the crystal filter performance. All other NC (Not Connected) type pins are also
recommended to be connected to VSS to minimize noise coupling.
3) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced (modulated)
-
the output is a current source/sink with |IOUT| > 5 µA
at power down the output is pulled to VSS (pull down switch)
-
4) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (working)
Internal pull-up with current < 1 µA which is switched off at power down
5) PDN = VSS means receiver on; PDN = VDD means receiver off
-
-
Fast start-up is triggered when the receiver is after power down (PDN=VDD) controlled to power up
(PDN=VSS) i.e. at the falling edge of PDN signal.
6) Receiver inputs RFIP and RFIM have both 1.4 MΩ biasing resistors towards VDD
10 (14)
MAS [ MICRO ANALOG SYSTEMS ]
