DA6116.010
5 October, 2017
Figure 1. Normal write to both channels (command CBh=%1100 1011, don’t care bits 1) with written byte
AAh=%1010 1010.
The same process takes place for reading the information. XCS will remain low for next 16 CCLK pulses. The first
8 bits containing read address are shifted in on the rising edges of the 8 CCLK pulses. MAS6116 starts to drive
first read bit to DATA line at falling edge of the 8th CCLK pulse. Thus controller should release the DATA line
between rising and falling edges of the 8th CCLK pulse to avoid race situation. The controller can read the bits on
the rising edge of CCLK pulses. The first bit is read on the rising edge of the 9th CCLK pulse. MAS6116 shifts a
new bit to DATA line at each new falling edge of the CCLK line. The last bit is read on the rising edge of the 16th
CCLK pulse. After minimum hold time (THLCHS) the XCS must be returned to high. When XCS is high, the DATA
pin is in high impedance state, which enables DATA pins of other devices to be connected together. See figure 2
example of serial interface signals during Read left channel (command EFh=%1110 1111, don’t care bits 1) with
read byte AAh=%1010 1010.
Figure 2. Read left channel (command EFh=%1110 1111, don’t care bits 1) with read byte AAh=%1010 1010.
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MAS [ MICRO ANALOG SYSTEMS ]
