DA1017.002
29 May, 2002
SAMPLES IN SBDIL 20 PACKAGE
NC
1
20 VSS
19 NC
18 RFI
17 PDN
16 NC
15 QO
14 NC
13 QI
12 NC
11 NC
VDD 2
NC
3
DEC 4
AGC
NC
5
6
PUP 7
DCF 8
NC
NC
9
10
PIN DESCRIPTION
Pin Name
NC
VDD
NC
DEC
AGC
NC
PUP
DCF
NC
NC
NC
NC
QI
NC
QO
NC
PDN
RFI
NC
VSS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Type
P
AO
AO
AI
DO
Function
Positive power supply
Demodulator capacitor
AGC capacitor
Power up input
Demodulator output
1
2
Note
AI
AO
AI
AI
G
Quartz filter input
3
Quartz filter output
Power down input
Receiver input
Power supply ground
4
Notes:
1) See power down control table on page 2.
-
Internal pull-down resistor > 1 MΩ to VSS
2) DCF = VSS when carrier amplitude at maximum; DCF = VDD when carrier amplitude is reduced (25%
modulated)
-
the output is a current source/sink with |I
OUT
| > 5
µA
-
at power down the output is high impedance
3) Pin 14 between quartz crystal filter pins must be connected to VSS to eliminate package leadframe parasitic
capacitances disturbing the crystal filter performance. All other NC (Not Connected) pins are also
recommended to be connected to VSS to minimize noise coupling.
4) See power down control logic table on page 2.
- Internal pull-up resistor > 1MΩ to VDD
5(6)
MAS [ MICRO ANALOG SYSTEMS ]
