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88EM8040XX-SAG2C000 参数 Datasheet PDF下载

88EM8040XX-SAG2C000图片预览
型号: 88EM8040XX-SAG2C000
PDF下载: 下载PDF文件 查看货源
内容描述: 功率因数校正控制器的反激式拓扑结构 [Power Factor Correction Controller for Flyback Topology]
分类和应用: 功率因数校正光电二极管控制器
文件页数/大小: 48 页 / 445 K
品牌: MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
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Design and Applications Information  
Isolated Voltage Loop and Output Voltage Feedback on FB Pin  
5.2.3  
RS2 and Rf1 Design  
The RS2 and Rf1 design is mainly based on the opto-couplers current transfer ratio(CTR) Which  
should be around 100% to 200%. RS2 is designed to produce around 1mA current at the LED side  
of the opto-coupler. Rf1 is designed to produce 2.5V feedback voltage to close the loop under a  
stead state. If Rf1 is designed at 1.24k, the current at transistor side of the opto-coupler should be  
designed at 2mA (typical). This should have enough signal to noise ratio in the practical design. The  
feedback resistor (Rf1) should be kept close to the opto-coupler to avoid noise in the layout.  
The output of PFC Flyback has double line frequency ripple voltage. At the steady state operation  
condition, the FB pin voltage transferred from secondary side also has this double line frequency  
ripple voltage. The ripple voltage amplitude on the FB pin is determined by the output voltage ripple  
amplitude and the gain from the output voltage to the FB pin (referred in the previous section  
Section 5.2.2, Compensation Network Design, on page 31). It is noticed that there is an attenuated  
ripple appearing at the output of the amplifier with the minus phase shift from the output voltage  
ripple. Therefore, the ratio of ripple voltage amplitude over the DC voltage value of FB pin is bigger  
than the ratio of output ripple over DC output voltage. If the output ripple voltage is too big in certain  
applications, the FB pin voltage peak value might trigger the internal FB OVP threshold, which is  
about 7% on the top of the reference value. This will heavily distort the input current waveform and  
disturb the stability of the system. In order to solve this issue, it is recommended to use a constant  
offset voltage circuit, as show in Figure 22. This circuit consists of a diode (ZD1), and two resistors  
(Rf2 and Rf3). This will provide a bias current from the bias winding so as to produce a bias voltage  
on the FB pin. Therefore, the ripple voltage amplitude of the FB pin is decreased below the FB OVP  
threshold. In the 90W reference design, the winding bias voltage provides 1mA (typical) offset  
current to the FB pin and the ripple voltage amplitude on the FB pin can decrease to be around half  
of that with this bias circuit. Rf2 can be calculated by equation (10), in which VFB is 2.5V reference  
voltage.  
If the cathode voltage VZD1 is 9.1V, Rf2 is calculated as 6.8kΩ⋅  
VZD1 VFB  
---------------------------  
= 1mA  
Equation (10)  
Rf2  
Figure 22: Bias Current for Offset Voltage on FB Pin  
OCP SW  
SGND  
VOut  
ISNS  
VIN  
PGND  
88EM8040  
/8041  
RS4  
CS2  
VDD  
FB  
CS1 RS5  
RS2  
Opto- Coupler  
VZD1  
R
f3  
Rf2  
Cvout  
CVCC  
CVDD  
R
f1  
+
Vref  
RS3  
ZD1  
Copyright © 2009 Marvell  
Doc. No. MV-S104983-01 Rev. A  
Page 33  
October 5, 2009, Preliminary  
Document Classification: Proprietary