Design and Applications Information
Input Voltage Resistor Divider on VIN Pin
5
Design and Applications Information
The boost converter is the most popular topology for two stage front-end PFC pre-regulator system.
The 88EM8010/88EM8011 chip control algorithm uses Average Current Mode Control for power
factor correction applications based on Boost topology with low harmonic distortion and good noise
immunity. The IC senses the output voltage and forces it to follow the reference voltage to produce a
stable DC output voltage matching the design requirement. It also senses the inductor current and
forces the average signal of the inductor current to follow the sinusoidal current reference, therefore
achieving unity power factor.
Marvell's innovative PFC control technology improves the performance of the Boost converter used
in PFC applications. The 88EM8010/88EM8011 provides the higher drive current capability than that
of the competitors' ICs. The 88EM8010/8011 also achieves high power factor/low THD at high line
low load condition which is benefited from Marvell mixed signal technology. The Boost PFC solution
based on the 88EM8010/88EM8011 provides customers with the simplest structure, lowest cost and
best performance compared with the other industry solutions currently on the market.
The following sections provide guidelines for the application design, component selection, and board
layout in order to improve front-end Boost PFC performance. There are three analog input signals
listed below are required from the power train to the controller IC 88EM8010/88EM8011.
1. Input voltage signal at VIN pin is a half sinusoidal waveform. It is fed into the VIN pin through
the input voltage resistor divider. This is for the line frequency zero-cross detection for PFC.
2. Output voltage signal at FB pin is the output voltage through the resistor divider to feedback on
FB pin. This is for the voltage loop regulation.
3. Current sensing signal through the sensing resistor to the ISNS pin. This is for the average
current mode control to achieve a good sinusoidal current waveform and high power factor.
The output signal from the 88EM8010/88EM8011 is the PWM gate drive signal from the SW pin. The
switching frequency on the 88EM8010 device is fixed to 60kHz (typical) while the 88EM8011 is fixed
to 120kHz (typical). Both device tolerances are shown in Table 5, Electrical Characteristics, on
page 15.
5.1
Input Voltage Resistor Divider on VIN Pin
An accurate peak detection signal and zero-cross detection for regenerating the input sinusoidal
voltage is the most important issue for a proper current shaping and total harmonic distortion (THD)
improvement. If the threshold reference is too high, near the peak area, the calculation may lose
accuracy because of the low slope. On the other hand, if the threshold reference is too low due to
the possible distortions near the zero-crossing, there could be an error on zero-cross detection. For
a universal input voltage range (85VAC~270VAC) the optimum accuracy would be achieved if the
threshold level is around 30 degree of the line cycle.
Copyright © 2009 Marvell
September 30, 2009, 2.00
Doc. No. MV-S104861-01 Rev. –
Page 27
Document Classification: Proprietary
MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
