®
LY61L51216A
512K X 16 BIT HIGH SPEED CMOS SRAM
Rev. 1.3
WRITE CYCLE 3 (LB#,UB# Controlled)
(1,2,5,6)
tWC
Address
tAW
tWR
CE#
tAS
tCW
tBW
LB#,UB#
tWP
WE#
tWHZ
High-Z
Dout
(4)
tDW
tDH
Din
Data Valid
Notes :
1.WE#,CE#, LB#, UB# must be high during all address transitions.
2.A write occurs during the overlap of a low CE#, low WE#, LB# or UB# = low.
3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed
on the bus.
4.During this period, I/O pins are in the output state, and input signals must not be applied.
5.If the CE#, LB#, UB# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state.
6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
DATA RETENTION CHARACTERISTICS
PARAMETER
SYMBOL
TEST CONDITION
MIN.
TYP.
MAX.
UNIT
VCC for Data Retention
VDR CE# ≧ VCC - 0.2V
CC = 1.5V
1.5
-
3.6
V
V
CE# ≧VCC - 0.2V;
Other pin is at 0.2V or
Vcc-0.2V
-
-
Data Retention Current
IDR
3
25
mA
Chip Disable to Data
Retention Time
Recovery Time
See Data Retention
Waveforms (below)
tCDR
tR
0
-
-
-
-
ns
ns
tRC
*
tRC = Read Cycle Time
*
DATA RETENTION WAVEFORM
VDR ≧ 1.5V
Vcc(min.)
Vcc
Vcc(min.)
tCDR
tR
VIH
CE# ≧ Vcc-0.2V
VIH
CE#
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, lndustry E . Rd. 9, Science-Based Industrial Park, Hsinchu 300, Taiwan
TEL: 886-3-6668838
FAX: 886-3-6668836
7
LYONTEK [ Lyontek Inc. ]
