LY61L102516A
1024K X 16 BIT HIGH SPEED CMOS SRAM
Rev. 1.3
DATA RETENTION CHARACTERISTICS
PARAMETER
VCC for Data Retention
SYMBOL
TEST CONDITION
CE# ≧ VCC - 0.2V or CE2 ≦ 0.2V
VCC = 1.5V
MIN. TYP. MAX. UNIT
VDR
1.5
-
3.6
V
Data Retention Current
IDR
CE# ≧ VCC - 0.2V or CE2 ≦ 0.2V
Other pins at 0.2V or VCC-0.2V
-
4
40
mA
Chip Disable to Data
Retention Time
Recovery Time
tCDR
tR
See Data Retention Waveforms (below)
0
-
-
-
-
ns
ns
tRC*
tRC* = Read Cycle Time
DATA RETENTION WAVEFORM
Low VCC Data Retention Waveform (1) (CE# controlled)
VDR ≧ 1.5V
Vcc(min.)
Vcc
Vcc(min.)
tCDR
tR
VIH
CE# ≧ Vcc-0.2V
VIH
CE#
Low VCC Data Retention Waveform (2) (CE2 controlled)
VDR ≧ 1.5V
Vcc(min.)
Vcc
Vcc(min.)
tCDR
tR
CE2 ≦ 0.2V
CE2
VIL
VIL
Lyontek Inc. reserves the rights to change the specifications and products without notice.
2F, No.17, lndustry E . Rd.II, Science-Based Industrial Park, Hsinchu 300, Taiwan
TEL: 886-3-6668838
FAX: 886-3-6668836
11
LYONTEK [ Lyontek Inc. ]
