LY61L102516A
1024K X 16 BIT HIGH SPEED CMOS SRAM
Rev. 1.3
WRITE CYCLE 3 (LB#,UB# Controlled) (1,4,5)
tWC
Address
tAW
tWR
CE#
tAS
tCW
CE2
tBW
LB#,UB#
tWP
WE#
Dout
tWHZ
High-Z
(4)
tDW
tDH
Din
Data Valid
Notes :
1.A write occurs during the overlap of a low CE#, high CE2, low WE#, LB# or UB# = low.
2.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed
on the bus.
3.During this period, I/O pins are in the output state, and input signals must not be applied.
4.If the CE#, LB#, UB# low transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain in
a high impedance state.
5.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
2F, No.17, lndustry E . Rd.II, Science-Based Industrial Park, Hsinchu 300, Taiwan
TEL: 886-3-6668838
FAX: 886-3-6668836
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LYONTEK [ Lyontek Inc. ]
