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LY61L1024GL-10T 参数 Datasheet PDF下载

LY61L1024GL-10T图片预览
型号: LY61L1024GL-10T
PDF下载: 下载PDF文件 查看货源
内容描述: [128K X 8 BIT HIGH SPEED CMOS SRAM]
分类和应用: 静态存储器
文件页数/大小: 17 页 / 512 K
品牌: LYONTEK [ Lyontek Inc. ]
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®
LY61L1024  
128K X 8 BIT HIGH SPEED CMOS SRAM  
Rev. 2.7  
TIMING WAVEFORMS  
READ CYCLE 1 (Address Controlled) (1,2)  
tRC  
Address  
Dout  
tAA  
tOH  
Previous Data Valid  
Data Valid  
READ CYCLE 2 (CE# and CE2 and OE# Controlled) (1,3,4,5)  
tRC  
Address  
tAA  
CE#  
tACE  
CE2  
OE#  
tOE  
tOLZ  
tOH  
tOHZ  
tCHZ  
tCLZ  
High-Z  
High-Z  
Dout  
Data Valid  
Notes :  
1.WE# is high for read cycle.  
2.Device is continuously selected OE# = low, CE# = low., CE2 = high.  
3.Address must be valid prior to or coincident with CE# = low, CE2 = high; otherwise tAA is the limiting parameter.  
4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.  
5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
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