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SXT6051 参数 Datasheet PDF下载

SXT6051图片预览
型号: SXT6051
PDF下载: 下载PDF文件 查看货源
内容描述: [Terminator, 1-Func, CMOS, PQFP208, PLASTIC, QFP-208]
分类和应用: ATM异步传输模式电信电信集成电路
文件页数/大小: 144 页 / 895 K
品牌: LevelOne [ LEVEL ONE ]
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SXT6051 Pin Assignments And Signal Description  
Table 2: Signal Description (Sheet 2 of 11)  
Pin #  
Name  
Type  
Description  
External References  
Internal TX Frame Alignment Output. This signal is syn-  
185  
186  
163  
187  
MFRMO  
O
HiZ-4ma  
chronous with the multiplexer frame and is used to synchronize  
other transmitters. See Figures 12 and 13.  
MFRMI  
LOS  
I
External TX Frame Alignment Input. An 8 KHz signal used  
to align the start of a transmit multiplexer frame. If not needed,  
this input is grounded.  
TTLin  
I
Loss of Signal Input. Input from the Line Interface circuit that  
can be used either with a parallel interface or with a serial inter-  
face. Active High.  
TTLin  
MHICLK  
I
Multiplexer System Serial Clock. An external STM-0 (51.84  
MHz) reference frequency input for the multiplexer and can be  
used by the demultiplexer section during Blue Signal /AIS Sig-  
nal generation.  
TTLin  
188  
86  
MHBCLKI  
MMFRMI  
I
Multiplexer System Parallel Clock. An external STM-0 (6.48  
MHz) or STM-1 (19.44 MHz) reference frequency input for the  
multiplexer and can be used by the demultiplexer section dur-  
ing Blue Signal /AIS Signal generation.  
TTLin  
I
External Multiframe Alignment. A 2 KHz input signal (25%  
duty cycle) that can be used, in terminal mode only, to reset the  
internal H4 byte counter.  
TTLin  
192  
191  
113  
MMSAJ1EN  
MMSAPAYEN  
DRETFRMI  
O
Test Point For J1 Position on TX framed signal. Provided for  
testing purposes.  
HiZ-2ma  
O
Test point for Payload Enable on TX framed signal. Provided  
for testing purposes.  
HiZ-2mA  
I
Demultiplexer Receive Re-timing Frame. An 8 KHz pulse  
synchronous with DRETCLK, used by the receive re-timing  
function to synchronize the position of the VC3 or VC4 pay-  
load. It is always needed.  
TTLin  
112  
DRETCLK  
I
Demultiplexer Receive Re-timing Clock Synchronization. A  
parallel clock input at either 6.48 MHz (STM-0) or 19.44 MHz  
(STM-1). It is used to generate the clocking for the VC-3 or  
VC-4 container on DTBDATA<7:0> when the retiming func-  
tion is enabled.  
TTLin  
Serial Overhead Byte Access  
15  
16  
TSOH  
I
Transmit RSOH and MSOH Serial Access. Input for serially  
sourced RSOH and MSOH transmit data. The data is clocked  
in synchronous to MMSPPCKO at 19.44 MHz for STM-1 and  
6.48 MHz for STM-0.  
TTLin  
TSOHEN  
O
Transmit RSOH and MSOH Serial Access Clock Enable.  
Used to enable clocking of RSOH and MSOH data at the  
TSOH input using MMSPPCKO.  
HiZ-4ma  
9
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