Sterling-LWB5 Module
Datasheet
Control Signal Sequencing
The Sterling-LWB5 has two signals that allow host to control power consumption by enabling or disabling the
WLAN, Bluetooth and internal regulator blocs. The timing values indicated are minimum required values; longer
delays are also acceptable.
• WL_REG_ON: Used by the Power Management Unit (PMU) to power up the WLAN section. It is also OR-gated
with the BT_REG_ON input to control the internal DWM-W097 regulators. When this pin is high, the regulators
are enabled, and the WLAN section is out of reset. When this pin is low the WLAN section is in reset. If both
WL_REG_ON and BT_REG_ON pins are low, the regulators are disabled.
• BT_REG_ON: Used by the Power Management Unit (PMU) (OR-gated with WL_REG_ON) to power up the
internal DWM-W097 regulators. If both the BT_REG_ON and WL_REG_ON pins are low, the regulators are
disabled. When this pin is low the Bluetooth section is in reset.
Note:
For both pins, there should be at least a 10ms time delay between consecutive toggles (when both signals have
been driven low). This is to allow timer for the CBUCK regulator to discharge. If this delay is not followed, then
there may be a VDDIO in-rush current on the order of 36mA during next PMU cold start. The Sterling-LWB5 has
an internal power on reset (POR) circuit. The device will be held in reset for a maximum of 110ms after VBAT
and VDDIO have both passed the POR threshold. Wait at least 150ms after VBAT and VDDIO are available
before initiating SDIO access.
The information in this document is subject to change without notice.
330-0208-R2.1
Copyright © 2016-2018 LSR
Page 31 of 80
LSTD [ Laird Connectivity ]
