LF3338
DEVICES INCORPORATED
8-Bit Vertical Digital Image Filter
parallel. This allows all the line buffers Cascading
FUNCTIONAL DESCRIPTION
to be preloaded with data in the
amount of time it normally takes to
load a single line buffer.
Line Buffers
A cascade port is provided to allow
cascading of multiple devices for
more filter taps (see Figure 5).
COUT7-0 of one device should be
connected to DIN7-0 of another
device. As many LF3338s as desired
may be cascaded together. How-
ever, the outputs of the LF3338s
must be added together with exter-
nal adders.
The maximum delay length of each line
buffer is 3076 cycles and the minimum
is 4 cycles. Configuration Register 0
(CR0) determines the delay length of
the line buffers. The line buffer length
is equal to the value of CR0 plus 4. A
value of 0 for CR0 sets the line buffer
length to 4. A value of 3072 for CR0
sets the line buffer length to 3076. Any
values for CR0 greater than 3072 are not
valid.
Odd and Even Field Filtering
The LF3338 is capable of odd and even
field filtering. Bit 2 of Configuration
Register 1 enables the VB Data Input
port required for odd and even field
filtering. Bit 3 of the same configura-
tion register enables the line buffer in
the VB Data path. Line buffer length is
set to the length written to Configura-
tion Register 0. If line buffer parallel
load is enabled and odd and even field
The first line buffer on a cascaded
device must have its length short-
ened by two delays. This is to
The line buffers have two modes of
operation: delay mode and recirculate
account for the added delays of the
input register on the device and the
cascade output register from the
previous LF3338. If Bit 0 of Con-
figuration Register 3 is set to “1”,
the length of the first line buffer will
be reduced by two. This will make
its effective length the same as the
other line buffers on the device. If
Bit 0 of Configuration Register 3 is
set to “0”, the length of the first line
buffer will be the same as the other
line buffers. When cascading
mode. Bit 0 of Configuration Register 1 filtering is enabled, the data for the VB
determines which mode the line buffers line buffer comes from the VB Data
are in. In delay mode, the data input to Input port.
the line buffer is delayed by an amount
determined by CR0. In recirculate
mode, the output of the line buffer is
routed back to the input of the line
buffer allowing the line buffer contents
to be read multiple times.
Interleaved Data
The LF3338 is capable of handling
interleaved data. The number of data
sets it can handle is determined by the
number of data values contained in a
video line. If the interleaved video line
has 3076 data values or less, the LF3338
can handle it no matter how many data
sets are interleaved together.
Bit 1 of Configuration Register 1 allows
the line buffers to be loaded in parallel.
When Bit 1 is “1”, the input register
(DIN7-0) loads all seven line buffers in
devices, the first LF3338 should
have Bit 0 of Configuration Register
FIGURE 5.
MULTIPLE LF3338S CASCADED TOGETHER
LF3338
LF3338
LF3338
LF3338
8
COUT
DIN
COUT
DIN
COUT
DIN
DIN
LINE BUFFERS
LINE BUFFERS
LINE BUFFERS
LINE BUFFERS
VERTICAL FILTER
VERTICAL FILTER
VERTICAL FILTER
VERTICAL FILTER
RSL
RSL
RSL
RSL
CIRCUIT
CIRCUIT
CIRCUIT
CIRCUIT
LF3347
25
25
RSL
CIRCUIT
16
DATA OUT
29 TAP RESULT
Video Imaging Products
04/06/1999–LDS.3338-B
5
LOGIC [ LOGIC DEVICES INCORPORATED ]
