LF3338
DEVICES INCORPORATED
8-Bit Vertical Digital Image Filter
SIGNAL DEFINITIONS
Power
FIGURE 2. INPUT FORMATS
Input Data
Coefficient Data
VCC and GND
7
6
5
2
1
0
11 10 9
2
1
0
+3.3 V power supply. All pins must be
connected.
–27 26 25
22 21 20
–20 2–1 2–2
2–9 2–10 2–11
(Sign)
(Sign)
Clock
CLK — Master Clock
TABLE 1. OUTPUT FORMATS
The rising edge of CLK strobes all
enabled registers.
SLCT4-0
00000
00001
00010
S15 S14 S13
F15 F14 F13
F16 F15 F14
F17 F16 F15
· · ·
· · ·
· · ·
· · ·
S8
F8
F9
S7
F7
F8
· · ·
S2
F2
F3
F4
S1
F1
F2
F3
S0
F0
F1
F2
· · ·
· · ·
· · ·
Inputs
DIN7-0 — Data Input
F10 F9
DIN7-0 is the 8-bit registered data input
port. Data is latched on the rising edge
of CLK.
·
·
·
· · ·
· · ·
· · ·
· ·
· ·
· ·
· · ·
· · ·
· · ·
01110
01111
10000
F29 F28 F27
F30 F29 F28
F31 F30 F29
· · ·
· · ·
· · ·
F22 F21
F23 F22
F24 F23
· · ·
· · ·
· · ·
F16 F15 F14
F17 F16 F15
F18 F17 F16
VB7-0 — Field Filtering Data Input
VB7-0 is the 8-bit registered data input
port used only when implementing
Odd and Even Field Filtering (see
Functional Description section for a full
discussion). Data is latched on the
rising edge of CLK.
COUT7-0 — Cascade Data Output
FIGURE 3. ACCUMULATOR FORMAT
COUT7-0 is a 8-bit cascade output
port. COUT7-0 on one device
should be connected to DIN7-0 of
another LF3338.
Accumulator Output
CF11-0 — Coefficient Input
31 30 29
2
1
0
–216 215 214
2–13 2–14 2–15
CF11-0 is used to load data into the
coefficient banks and configuration/
control registers. Data present on
CF11-0 is latched into the LF InterfaceTM
on the rising edge of CLK when LD is
LOW (see the LF InterfaceTM section for
a full discussion).
(Sign)
Controls
LD — Coefficient Load
PAUSE — LF InterfaceTM Pause
When LD is LOW, data on CF11-0
is latched into the LF InterfaceTM
on the rising edge of CLK. When
LD is HIGH, data can not be
When PAUSE is HIGH, the LF
InterfaceTM loading sequence is halted
until PAUSE is returned to a LOW
state. This effectively allows the user
to load coefficients and control
registers at a slower rate than the
master clock (see the LF InterfaceTM
section for a full discussion).
CA7-0 — Coefficient Address
latched into the LF InterfaceTM
.
When enabling the LF InterfaceTM
for data input, a HIGH to LOW
transition of LD is required in
order for the input circuitry to
function properly. Therefore, LD
must be set HIGH immediately
after power up to ensure proper
operation of the input circuitry
(see the LF InterfaceTM section for
a full discussion).
CA7-0 determines which row of data in
the coefficient banks is fed to the
multipliers. CA7-0 is latched into the
Coefficient Address Register on the
rising edge of CLK when CEN is LOW.
CEN — Coefficient Address Enable
Outputs
When CEN is LOW, data on CA7-0 is
latched into the Coefficient Address
Register on the rising edge of CLK.
When CEN is HIGH, data on CA7-0 is
not latched and the register’s contents
will not be changed.
DOUT15-0 — Data Output
DOUT15-0 is the 16-bit registered data
output port.
Video Imaging Products
04/06/1999–LDS.3338-B
3
LOGIC [ LOGIC DEVICES INCORPORATED ]
