LF3330
DEVICES INCORPORATED
Vertical Digital Image Filter
limit is stored in bits 31-16. RSL3-0
determines which limit register is
used for limiting when limiting is
enabled. Configuration and control
register loading is discussed in the
LF InterfaceTM section.
LF InterfaceTM
LF InterfaceTM. When LD goes LOW,
the LF InterfaceTM is enabled for data
input. The first value fed into the
interface on CF11-0 is an address
which determines what the interface
is going to load. The three most
The LF InterfaceTM is used to load
data into the coefficient banks and
configuration/ control registers. LD
is u sed to enable and d isable the
FIGURE 10. ROUND REGISTER LOADING SEQUENCE WITH PAUSE IMPLEMENTATION
ROUND REGISTER
CLK
W1
PAUSE
LD
CF11-0
ADDR
1
DATA
1
DATA
2
DATA
3
DATA4
W1: Round Register loaded with new data on this rising clock edge.
FIGURE 11. LIMIT REGISTER LOADING SEQUENCE WITH PAUSE IMPLEMENTATION
LIMIT REGISTER
CLK
W1
PAUSE
LD
CF11-0
ADDR
1
DATA
1
DATA
2
DATA
3
DATA4
W1: Limit Register loaded with new data on this rising clock edge.
TABLE 10. COEFFICIENT BANK LOADING FORMAT
CF11
CF10
CF9
CF8
CF7
CF6
CF5
CF4
CF3
CF2
CF1
CF0
1st Word - Address
2nd Word - Bank 0
3rd Word - Bank 1
4th Word - Bank 2
5th Word - Bank 3
6th Word - Bank 4
7th Word - Bank 5
8th Word - Bank 6
9th Word - Bank 7
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
1
0
1
1
0
0
1
1
0
1
0
1
0
1
0
0
0
1
0
1
0
0
1
0
1
1
0
1
1
0
1
1
1
0
0
0
1
0
0
1
1
0
1
1
0
1
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
0
1
0
1
0
1
1
0
0
1
Video Imaging Products
11/08/2001–LDS.3330-M
8
LOGIC [ LOGIC DEVICES INCORPORATED ]
