LF3320
DEVICES INCORPORATED
Horizontal Digital Image Filter
NOTES
1. Maximum Ratings indicate stress input transition times less than 3 ns, measured tothe1.5Vcrossing point with
specifications only. Functional oper- output reference levels of 1.5 V (except
ation ofthese products at values beyond
datasheet loads. For the tDIS test, the
transition is measured to the ±200mV
tDIS test), and input levels of nominally
those indicated in the Operating Condi- 0 to 3.0 V. Output loading may be a level from the measured steady-state
tions table is not implied. Exposure to resistive divider which provides for ou tp u t voltage w ith ±10m A load s.
maximum rating conditions for ex-
tended periods may affect reliability.
The balancing voltage, VTH , is set at
3.0 V for Z-to-0 and 0-to-Z tests, and
specified IOH and IOL at an output
voltage of VOH min and VOL max
respectively. Alternatively, a diode set at 0 V for Z-to-1 and 1-to-Z tests.
2. The products described by this spec-
ification include internal circuitry de-
signedtoprotect the chipfrom damaging
substrate injection currents and accu-
mulations of static charge. Neverthe-
less, conventional precautions should
bridge with upper and lower current
sources of IOH and IOL respectively,
and a balancing voltage of 1.5 V may be
used. Parasitic capacitance is 30 pF
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.
minimum,and may be distributed.
be observed during storage, handling, This device has high-speed outputs ca-
and use ofthese circuits in order to avoid pable of large instantaneous current
exposure to excessive electrical stress pulses and fast turn-on/ turn-off times.
FIGURE A. OUTPUT LOADING CIRCUIT
values.
As a result, care must be exercised in the
testing of this device. The following
measuresarerecommended:
S1
DUT
3. This device provides hard clamping
of transient undershoot. Input levels
I
OL
V
TH
CL
below ground will be clamped begin- a. A 0.1 µF ceramic capacitor should be
ning at –0.6 V. The device can withstand
I
OH
installed between VCC and Ground
indefinite operation with inputs or out- leads as close to the Device Under Test
puts in the range of –0.5 V to +5.5 V. (DUT) as possible. Similar capacitors
FIGURE B. THRESHOLD LEVELS
Device operation will not be adversely
affected, however, input current levels and the tester common, and device
should be installed between device VCC
tENA
tDIS
OE
0
1.5 V
1.5 V
will be well in excess of 100 mA.
ground and tester common.
Z
Z
3.0V Vth
4. Actualtest conditions may vary from
those designated but operation is guar- be brought directly to the DUTsocket or
anteed as specified. contactor fingers.
b. Ground and VCC supply planes must
1.5 V
1.5 V
V
OL*
0.2 V
0.2 V
0
1
Z
Z
V
OH*
1
0V Vth
5. Supply current for a given applica- c. Input voltages on a test fixture should
tion can be accurately approximated be adjusted to compensate for inductive
V
OL
*
Measured VOL with IOH = –10mA and IOL = 10mA
V
OH
* Measured VOH with IOH = –10mA and IOL = 10mA
by:
ground and VCC noise to maintain re-
quired DUT input levels relative to the
DUT ground pin.
2
NCV F
where
4
10. Each parameter is shown as a mini-
mum or maximum value.Input require-
mentsarespecified from thepointofview
of the external system driving the chip.
Setup time,for example,is specified as a
minimum sincetheexternalsystem must
supply atleastthatmuch timetomeetthe
worst-case requirements of all parts.
Responsesfrom theinternalcircuitry are
specified from the point of view of the
device. Output delay, for example, is
specified as a maximum since worst-
case operation ofany device always pro-
vides data within that time.
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency
6. Tested with outputs changing every
cycle and no load,at a 40MHz clock rate.
7. Tested with all inputs within 0.1 V of
VCC or Ground, no load.
8. These parameters are guaranteed but
not 100% tested.
9. AC specifications are tested with
11. For the tENA test, the transition is
Video Imaging Products
08/16/2000–LDS.3320-N
2-23
LOGIC [ LOGIC DEVICES INCORPORATED ]
