LF3311
Horizontal / Vertical Digital Image Filter
DEVICES INCORPORATED
Improved Performance
Functional Description
Horizontal
Rounding
The horizontal filter output may be rounded by adding the contents of one of the sixteen horizontal round
registers to the horizontal filter output Wide Output Mode in the Operating Modes section). All programming
of the device is done through the Configuration Registers via the 16-bit Configuration/Control Interface.
(see Figure 7). Each round register is 32-bits wide and user-programmable. This allows the filter’s output to
be rounded to any precision required. Since any 32-bit value may be programmed into the round registers,
the device can support complex rounding algorithms as well as standard Half-LSB rounding. HRSL3-0
determines which of the sixteen horizontal round registers are used in the rounding operation. A value of
0 on HRSL3-0 selects horizontal round register 0. A value of 1 selects horizontal round register 1 and
so on. HRSL3-0 may be changed every clock cycle if desired. This allows the rounding algorithm to be
changed every clock cycle. This is useful when filtering interleaved data. If rounding is not desired, a round
register should be loaded with 0 and selected as the register used for rounding. Round register loading is
discussed in the LF Interface™ section.
Figure 6. Data Reversal
TXFRA/TXFRB
LIFO A
LIFO B
Horizontal Select
The word width of the horizontal filter output is 32-bits. However, only 12-bits may be sent to the filter output.
The horizontal filter select circuitry determines which 12-bits are passed (see Table 20). The horizontal
select registers control the horizontal select circuitry. There are sixteen horizontal select registers. Each
select register is 5-bits wide and user-programmable. HRSL3-0 determines which of the sixteen horizontal
select registers are used in the horizontal select circuitry. A value of 0 on HRSL3-0 selects horizontal select
register 0. A value of 1 selects horizontal select register 1 and so on. HRSL3-0 may be changed every
clock cycle if desired. This allows the 12-bit window to be changed every clock cycle. This is useful when
filtering interleaved data. Select register loading is discussed in the LF Interface™ section.
Horizontal Limiting An output limiting function is provided for the output of the horizontal filter. The horizontal limit registers
determine the valid range of output values when limiting is enabled (Bit 1 in Configuration Register 5). There
are sixteen 24-bit horizontal limit registers. HRSL3-0 determines which horizontal limit register is used
during the limit operation. A value of 0 on HRSL3-0 selects horizontal limit register 0. A value of 1 selects
horizontal limit register 1 and so on. Each limit register contains both an upper and lower limit value. If
the value fed to the limiting circuitry is less than the lower limit, the lower limit value is passed as the
filter output. If the value fed to the limiting circuitry is greater than the upper limit, the upper limit value
is passed as the filter output. HRSL3-0 may be changed every clock cycle if desired. This allows the
limit range to be changed every clock cycle. This is useful when filtering interleaved data. When loading
limit values into the device, the upper limit must be greater than the lower limit. Limit register loading is
discussed in the LF Interface™ section.
Video Imaging Products
LOGIC Devices Incorporated
6
9/19/05 LDS.3311-C
LOGIC [ LOGIC DEVICES INCORPORATED ]
