LF3311
Horizontal / Vertical Digital Image Filter
DEVICES INCORPORATED
Improved Performance
Functional Description
The horizontal filter is designed to filter a digital image in the horizontal dimension. This FIR filter can
be configured to have as many as 16-taps when symmetric coefficient sets are used and 8-taps when
asymmetric coefficient sets are used.
Horizontal Filter
ALU
The ALUs double the number of filter taps available, when symmetric coefficient sets are used, by pre-
adding data values which are then multiplied by a common coefficient (see Figure 4). The ALUs can
perform two operations: A+B and B–A. Bit 0 of Configuration Register 0 determines the ALU operation.
A+B is used with even-symmetric coefficient sets. B–A is used with odd-symmetric coefficient sets. Also,
either the A or B operand may be set to 0. Bits 1 and 2 of Configuration Register 0 control the ALU inputs.
A+0 or B+0 are used with asymmetric coefficient sets.
Figure 4. Symmetric Coefficient Set Examples
8
7 6 5
8
7
6
5
4
3
2
1
7
6
5
4
3
2
1
4 3 2 1
Even-Tap, Even-Symmetric
Coefficient Set
Odd-Tap, Even-Symmetric
Coefficient Set
Even-Tap, Odd-Symmetric
Coefficient Set
I/D Registers
The Interleave/Decimation Registers (I/D Registers) feed the ALU inputs. They allow the device to filter up
to sixteen data sets interleaved into the same data stream without having to separate the data sets. The I/D
Registers should be set to a length equal to the number of data sets interleaved together. For example, if
two data sets are interleaved together, the I/D Registers should be set to a length of two. Bits 1 through 4 of
Configuration Register 1 determine the I/D Register length.
The I/D Registers also facilitate using decimation to increase the number of filter taps. Decimation by N
is accomplished by reading the horizontal filter’s output once every N clock cycles. The device supports
decimation up to 16:1. With no decimation, the maximum number of filter taps is sixteen. When decimating
by N, the number of filter taps becomes 16N because there are N–1 clock cycles when the horizontal filter’s
output is not being read. The extra clock cycles are used to calculate more filter taps.
When decimating, the I/D Registers should be set to a length equal to the decimation factor. For example,
when performing a 4:1 decimation, the I/D Registers should be set to a length of four. When not decimating
or when only one data set (non-interleaved data) is fed into the device, the I/D Registers should be set
to a length of one.
HSHEN enables or disables the loading of data into the forward and reverse I/D Registers when the device
is in Dimensionally Separate Mode (see the HSHEN section for a full discussion). When in Orthogonal
Mode, HSHEN also enables or disables the loading of data into the input register (DIN11-0) and the line
buffers.
It is important to note that in Orthogonal Mode, either HSHEN or VSHEN can disable the loading of data
into the input register (DIN11-0), I/D Registers, and line buffers. Both must be active to enable data loading
in Orthogonal Mode.
Video Imaging Products
LOGIC Devices Incorporated
4
9/19/05 LDS.3311-C
LOGIC [ LOGIC DEVICES INCORPORATED ]
