ADVANCE INFORMATION
L9D345G72BG5
4.5 Gb, DDR3, 64 M x 72 Integrated Module (IMOD)
T
ABLE
3 - B
ALL
/S
IGNAL
L
OCATION AND
D
ESCRIPTION
Ball Assignments
B7, B10, C7, C10,
C9, C8, B9, B8,
A10, A7, A8, A9,
D7
Symbol
A
0,
A
1,
A
2,
A
3,
A
4,
A
5,
A
6,
A
7,
A
8,
A
9,
A
10
/AP, A
11,
A
12
/BC
Type
Description
address and auto precharge bit (A10) for READY/WRITE commands, to select one location
out of the memory array in the respective bank. A10 sampled during a PRECHARGE com-
mand determines whether the PRECHARGE applies to one bank (A10 LOW), bank selected
by BA[2:0] or all banks (A10 HIGH). The address inputs also provide the op-code during a
LOAD MODE command. Address inputs are referenced to VrefCA. A12/BC#: when enabled
in the mode register (MR), A12 is sampled during READ and WRITE commands to determine
whether burst chop, LOW = BC4 burst chop).
Input Address Inputs:
Provide the ROW address for ACTIVATE commands, and the column
E8, E9, D9
BA
0
, BA
1,
BA
2
Input Bank Address Inputs:
BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or
PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1,
MRE, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to VrefCA.
D10, D8
F4, G5,
F16, G15,
L13, K12,
L2, K1,
M8, N6
G4, G16,
K13, K2,
M6
RFU
CLK
0
, CLK
0
\,
CLK
1
, CLK
1
\,
CLK
2
, CLK
2
\,
CLK
3
, CLK
3
\,
CLK
4
, CLK
4
\
CKE
0,
CKE
1
,
CKE
2
, CKE
3
,
CKE
4
Input
Future Address: A13, A14
Input Clock:
CKx and CKx\ are differential clock inputs, one differential pair per WORD,
five
WORDs contained in the L9D3xxG72 product. All control and address input signals are sam-
pled on the crossing of the positive edge of CKx and the negative edge of CKx\. Output data
strobes (UDQSx/UDQSx\ and LDQSx/LDQSx\) is referenced to the crossing of CKx and CKx\.
Input Clock Enable:
CKE enables and disables internal circuitry and clocks on the SDRAM. The
specific circuitry that is enabled/disabled is dependent upon the DDR3 SDRAM configura-
tion and operating mode. Taking CKE LOW provides PRECHARGE power-down and SELF
REFRESH operations (all banks idle), or active power-down (row active in any bank). CKE is
synchronous for power-down entry and exit and for self refresh entry. CKE is asynchronous
for self refresh exit. Input buffers (excluding CKx, CKx\, CKE, RESET#, and ODT) are disabled
during SELF REFRESH. CKE is referenced to VrefCA.
G1, G13,
K16, K4,
M12
CS
0
\, CS
1
\,
CS
2
\, CS
3
\,
CS
4
\
Input Chip Select:
CS\ enables (registered LOW) and disables the command decoder. All com-
mands are masked when CS\ is registered HIGH. CS\ provides for external rank selection on
systems with multiple ranks. CS\ is considered part of the command code. CS\ is referenced
to VrefCA.
E2, E4,
E13, F15,
M15, M13,
M5, M2,
N11
G2, F12, K15,
L5, M11
F1, G12, L16,
L4, M9
F2, F13, L15,
M4, M10
LDMx, UDMx,
LDMx, UDMx,
LDMx, UDMx,
LDMx, UDMx
LDMx
Input Input Data Mask:
LDMx is the Lower-byte of a WORD, UDMx is the Upperbyte of a WORD,
the L9D3xxG72 contains
five
WORDS. The data mask input, masks WRITE data. Lower byte
data masked when LDMx is sampled HIGH, upper byte data masked when UDMx is sampled
HIGH. The UDMx and LDMx pins are structured as inputs only, the pins electrical loading is
designed to match that of the DQ and LDQSx, LDQSx\, UDQSx, and UDQSx\ pins.
RAS0\, RAS1\, RAS2\,
Input ROW Address Strobe/Select:
Defines the command being entered along CAS\, WE\, and
RAS3\, RAS4\
CS\. This input pin is referenced to VrefCA.
CAS0\, CAS1\, CAS2\,
Input COLUMN Address Strobe/Select:
Defines the command being entered along with RAS\,
CAS3\, CAS4\
WE\, and CS\. This input pin is referenced to VrefCA.
WE
0
\, WE
1
\, WE
2
\, Input WRITE Enable Input:
Defines the command being entered along with CAS\, RAS\,, and CS\.
WE
3
\, WE
4
\
This input pin is referenced to VrefCA.
LOGIC Devices Incorporated
www.logicdevices.com
8
High Performance, Integrated Memory Module Product
Jul 06, 2009 LDS-L9D345G72BG5-A
LOGIC [ LOGIC DEVICES INCORPORATED ]
