欢迎访问ic37.com |
会员登录 免费注册
发布采购

L9D345G72BG5E19 参数 Datasheet PDF下载

L9D345G72BG5E19图片预览
型号: L9D345G72BG5E19
PDF下载: 下载PDF文件 查看货源
内容描述: 4.5 GB, DDR3 , 64一M× 72集成模块( IMOD ) [4.5 Gb, DDR3, 64 M x 72 Integrated Module (IMOD)]
分类和应用: 双倍数据速率
文件页数/大小: 155 页 / 3349 K
品牌: LOGIC [ LOGIC DEVICES INCORPORATED ]
 浏览型号L9D345G72BG5E19的Datasheet PDF文件第8页浏览型号L9D345G72BG5E19的Datasheet PDF文件第9页浏览型号L9D345G72BG5E19的Datasheet PDF文件第10页浏览型号L9D345G72BG5E19的Datasheet PDF文件第11页浏览型号L9D345G72BG5E19的Datasheet PDF文件第13页浏览型号L9D345G72BG5E19的Datasheet PDF文件第14页浏览型号L9D345G72BG5E19的Datasheet PDF文件第15页浏览型号L9D345G72BG5E19的Datasheet PDF文件第16页  
ADVANCE INFORMATION L9D345G72BG5  
4.5 Gb, DDR3, 64 M x 72 Integrated Module (IMOD)  
TABLE 5: ABSOLUTE MAXIMUM RATINGS  
Symbol  
Parameter  
MIN  
MAX  
UNITS  
NOTES  
Vcc Supply Voltage relative to Vss  
Vcc Supply Voltage relative to VssQ  
Voltage on any pin relative to Vss  
Operating Case Temperature  
Operating Case Temperature  
Operating Case Temperature  
Storage Temperature  
-0.4  
1.975  
V
1
Vcc  
-0.4  
-0.4  
0
1.975  
1.975  
85  
1
V
VccQ  
V
1
VIN, VOUT  
TcIndustrial  
TcExtended  
TcMiltemp  
TSTG  
°C  
°C  
°C  
°C  
2,3  
2,3  
2,3  
2,3  
-40  
-55  
-55  
105  
125  
120  
NOTES:  
1. Vcc and VccQ must be within 300mV of each other at all times and VREF must not be greater than 0.6 x VccQ. When Vcc and  
VccQ are less than 500MV, VREF may be 300mV.  
2. Max operating case temperature. Tc is measured in the center of the package.  
3. Device Functionality is not guaranteed if the DRAM device exceeds the Maximum Tc during operation.  
TABLE 6: INPUT/OUTPUT CAPACITANCE  
Capacitance Parameter  
DDR3-800  
DDR3-1066  
DDR3-1333  
Symbol  
MIN MAX  
MIN  
3.1  
0
MAX MIN MAX UNITS NOTES  
6.2  
0.2  
3.0  
3.0  
0.2  
0.3  
0.3  
0.3  
5.3  
3.1  
0
6.2  
0.2  
3.0  
3.0  
0.2  
0.3  
0.3  
0.3  
5.5  
3.0  
0
6.1  
0.2  
2.5  
2.5  
0.2  
0.3  
0.3  
0.3  
5.1  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
CK and CK\  
CCK  
CDCK  
C: CK to CK\  
2
3
3
4
6
7
5
1.5  
1.5  
0
1.5  
1.5  
0
1.5  
1.5  
0
Single-end I/O: DQ, DM  
Differential I/O: DQS, DQS\  
C: DQS to DQS\  
C10  
C10  
CCCQS  
CDI0  
-0.5  
-0.5  
-0.5  
2.9  
-0.5  
-0.5  
-0.5  
2.9  
-0.5  
-0.5  
-0.5  
2.9  
C: DQ to DQS  
C: CNTL to CK  
CDI_CNTL  
CDI_CMD_ADDR  
CI_Shared  
C: cmd_ADDR to CK  
Inputs (RAS\, CAS\, WE\, CS\, CKE, ADDR)  
NOTES:  
1. Vcc = +1.5V± 0.075mV, VccQ = Vcc, VREF = Vss, f= 100MHz, Tc = 25°C, VOUT (DC) = 0.5 x VccQ, VOUT (peak to peak) = 0.1V  
2. DM input is grouped with I/O pins, reecting the signal is grouped with DQ and therefore matched in loading.  
3. CCCQS is for DQS vs. DQS\  
4. CDIO = CIO (DQ) - 0.5 x (CIO [DQS] + CIO [DQS\])  
5. Excludes CK, CK\  
6. CDI_CNTL = CI(CNTL) - 0.5 x (CCK[CK] + CCK [CK\]); CNTL = ODT, CS\ and CKE  
7. CDI_CMD_ADDR = CI (CMD_ADDR) - 0.5 x (CCK [CK] + CCK [CK\]); CMD = RAS\, CAS\, and WE\ ADDR = [n:0]  
LOGIC Devices Incorporated  
www.logicdevices.com  
High Performance, Integrated Memory Module Product  
12  
Jul 06, 2009 LDS-L9D345G72BG5-A