PreLIMINArY INforMAtIoN L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
REGISTER DEFINITION
Fig u r e 3 - ex t e n D e D mo D e re g is t e r
BA1 BA0 An . . . A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address bus
1
n + 2 n + 1 n . . .
9
8
7
6
5
4
3
2
1
0
Extended mode
register (Ex)
Operating Mode
0
1
DSDLL
DLL
E0
0
1
Enable
Disable
Mn + 2 Mn + 1 Mode Register Definition
0
0
1
1
0
1
0
1
Base mode register
Extended mode register
Reserved
2
Drive Strength
Normal
E1
0
1
Reduced
Reserved
3
En . . . E9 E8 E7 E6 E5 E4 E3 E2 E1, E0 Operating Mode
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
Valid
–
Reserved
Reserved
Notes: 1. n is the most significant row addres.s bit.
2. The reduced drive strength option is available only on Design Revision F and K.
3. The QFC# option is not supported.
ou t P u t Dr iv e st r e n g t h
Dll en a B l e /Dis a B l e
The DLL must be enabled for normal operation. The DLL enable is required
during power-up initialization and upon returning to normal operation after
having disabled the DLL for the purpose of debug or evaluation. When the
device exits SELF REFRESH mode, the DLL is enabled, 200 clock cycles
must occur before a READ command can be issued.
The normal full drive strength for all outputs are specified to be SSTL2,
Class II. The DDR IMOD supports an option for reduced drive. This option
is intended for the support of the lighter load and/or point-to-point environ-
ments. The selection of the reduced drive strength will alter the DQs and
DQSs from SSTL2, Class II drive strength to a reduced drive strength, which
is approximately 54% of the SSTL, Class II drive strength.
LOGIC Devices Incorporated
www.logicdevices.com
High Performance, Integrated Memory Module Product
11
Feb 2, 2009 LDS-L9D125G80BG4-C
LOGIC [ LOGIC DEVICES INCORPORATED ]
