L8C201/202/203/204
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Asynchronous FIFO
SWITCHING CHARACTERISTICS
Over Commercial and Industrial Operating Range
A
SYNCHRONOUS AND
R
ESET
T
IMING
(ns)
L8C201/202/203/204–
25
Symbol
t
RLRL
t
RLQV
t
RHRL
t
RLRH
t
RHQV
t
RHQZ
t
WLWL
t
WLWH
t
WHWL
t
DVWH
t
WHDX
t
SLSH
t
SLWL
t
WHSH
t
RHSH
t
SHWL
t
SLEL
t
SLHH
t
SLFH
Parameter
Read Cycle Time
(MHz)
Read Low to Output Valid
(Access Time)
Read High to Read Low
(Notes 8, 9)
Read Low to End of Read Cycle
(Notes 8, 9)
Read High to Output Valid
Read High to Output High Z
(Note 14)
Write Cycle Time
(Note 9)
Write Low to Write High
(Notes 8, 9)
Write High to End of Write Cycle
(Notes 8, 9)
Data Valid to Write High
(Notes 8, 9)
Write High to Data Change
(Notes 8, 9)
Reset Cycle Time
(Notes 9, 10)
Reset Low to Write Low
(Notes 9, 10)
Write High to Reset High
(Notes 9, 10)
Read High to Reset High
(Notes 9, 10)
Reset High to Write Low
(Notes 9, 10)
Reset Low to Empty Flag Low
Reset Low to Half-Full Flag High
Reset Low to Full Flag High
10
25
5
20
Min
35
25
10
15
5
15
Max
15
Min
25
15
8
12
5
15
Max
Min
20
12
5
10
5
15
15
10
5
8
0
10
15
10
10
5
12
12
12
10
10
10
12
Max
10
Min
15
10
Max
LE
35
25
25
10
25
25
25
t
RLRL
t
RHRL
t
RLRH
t
RLQV
t
RHQZ
DATA-OUT VALID
A
SYNCHRONOUS
R
EAD
R
BS
O
AND
W
RITE
O
PERATION
t
RLQV
t
RHQV
Q
8-0
DATA-OUT VALID
t
WLWL
t
WLWH
t
WHWL
W
t
DVWH
t
WHDX
D
8-0
DATA-IN VALID
R
ESET
T
IMING
O
t
SLWL
t
SLSH
t
WHSH
t
SHWL
RS
W
t
RHSH
R
t
SLEL
EF
t
SLHH
, t
SLFH
HF, FF
5
TE
35
25
10
15
0
25
15
10
10
0
20
12
8
8
0
25
15
25
15
15
10
15
15
15
12
20
12
12
8
DATA-IN VALID
FIFO Products
03/04/99–LDS.8C201/2/3/4-H