L7C108
PRELIMINARY INFORMATION L7C109
128K x 8 Static RAM
SWITCHING CHARACTERISTICS Over Operating Range
READ CYCLE Notes 5, 11, 12, 22, 23, 24 (ns)
L7C108/109
15/15-L 20/20-L 25/25-L 35/35-L 45/45-L
Symbol
tPD
Parameter
Min
Min
Min Max Min Max Min Max
Max
Max
Operation Recovery Time ꢁNotes 10, 19ꢃ
15
20
25
35
45
0
0
0
0
0
tCDR
Chip Enable High to Data Retention ꢁNote 10ꢃ
DATA RETENTION Notes 9, 10
DATA RETENTION MODE
V
CC
4.5 V
4.5 V
≥ 2 V
t
CDR
t
PD
CE
VIH
VIH
WRITE CYCLE Notes 5, 11, 12, 22, 23, 24 (ns)
L7C108/109
15/15-L 20/20-L 25/25-L 35/35-L 45/45-L
Min
Min
Min Max Min Max Min Max
Max
Max
Symbol Parameter
tAVAV
tELWH
tAVWL
tAVWH
tWHAX
tWLWH
tDVWH
tWHDX
tWHꢆX
tWLꢆZ
Write Cycle Time
35
45
15
12
0
20
12
0
25
20
0
Chip Enable Low to End of Write Cycle
Address Valid to Beginning of Write Cycle
Address Setup to End of Write Cycle
Address Hold After End Of Write
Write Enable Pulse Width Low
25
0
35
0
25
0
35
0
15
0
17
0
20
0
30
20
0
40
20
0
12
7
15
10
0
20
12
0
Data Setup to End of Write Cycle
Data Hold to End of Write
0
Write Enable High to Output Low Z ꢁNotes 20, 21ꢃ
Write Enable Low to Output High Z ꢁNotes 20, 21ꢃ
5
5
5
5
5
7
8
10
25
30
1M Static RAMs
LOGIC Devices Incorporated
www.logicdevices.com
5
Aug 11, 2010 LDS-L7C108/9-F
LOGIC [ LOGIC DEVICES INCORPORATED ]
