PRELIMINARY INFORMATION
L7C108
L7C109
128K x 8 Static RAM
SWITCHING CHARACTERISTICS
Over Operating Range
R
EAD
C
YCLE
Notes 5, 11, 12, 22, 23, 24 (ns)
L7C108/109
15/15-L 20/20-L 25/25-L
Symbol Parameter
t
AVAV
t
AV
t
AV
t
EL
t
EL
t
EH
t
GL
t
GL
t
GH
t
PU
V
X
V
X
Z
V
X
Z
35/35-L 45/45-L
35
45
35
3
3
35
3
3
15
15
0
0
15
0
0
20
20
20
45
45
Min Max Min Max Min Max Min Max Min Max
15
15
3
15
3
7
8
0
6
0
0
0
6
0
3
8
10
0
10
3
20
3
10
10
20
20
3
25
25
25
Read Cycle Time
Address Valid to Output Valid Notes 13, 14
Address Change to Output Change
Chip Enable Low to Output Valid Notes 13, 15
Chip Enable Low to Output Low Z Notes 20, 21
Chip Enable High to Output High Z Notes 20, 21
Output Enable Low to Output Valid
Output Enable Low to Output Low Z Notes 20, 21
Output Enable High to Output High Z Notes 20, 21
Input Transition to Power Up Notes 10, 19
R
EAD
C
YCLE
- A
DDRESS
C
ONTROLLED
Notes 13, 14
t
AVAV
ADDRESS
t
AVQV
DATA OUT
PREVIOUS DATA VALID
DATA VALID
t
AVQX
t
PU
I
CC
t
PD
R
EAD
C
YCLE
- CE/OE C
ONTROLLED
N
OTES
13, 15
CE
t
AVAV
t
ELQV
t
ELQX
t
EHQZ
OE
t
GLQX
DATA OUT
HIGH IMPEDANCE
t
GLQV
DATA VALID
t
GHQZ
HIGH
IMPEDANCE
t
PU
Icc
50%
t
PD
50%
LOGIC Devices Incorporated
www.logicdevices.com
4
1M Static RAMs
Aug 11, 2010 LDS-L7C108/9-F
LOGIC [ LOGIC DEVICES INCORPORATED ]
