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L2340QC20 参数 Datasheet PDF下载

L2340QC20图片预览
型号: L2340QC20
PDF下载: 下载PDF文件 查看货源
内容描述: 数字频率合成器 [Digital Synthesizer]
分类和应用:
文件页数/大小: 11 页 / 270 K
品牌: LOGIC [ LOGIC DEVICES INCORPORATED ]
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L2340  
DEVICES INCORPORATED  
Digital Synthesizer  
Outputs  
L2340 FUNCTIONAL BLOCK DIAGRAM  
I15-0 — x-coordinate Data Output  
AM14-0  
ENA  
PH31-0  
ENP1-0  
2
FM  
PM  
I15-0 is the 16-bit Cartesian x-coordi-  
nate Data output port. When OEI is  
HIGH, I15-0 is forced into the high-  
impedance state. I15 is forced HIGH if  
OBIQ is LOW.  
15  
32  
32  
M
C
AM  
Q15-0 — y-coordinate Data Output  
Q15-0 is the 16-bit Cartesian y-coordi-  
nate Data output port. When OEQ is  
HIGH, Q15-0 is forced into the high-  
impedance state. Q15 is forced HIGH  
if OBIQ is LOW.  
32  
PM  
FM  
32  
32  
24  
24  
Controls  
15  
15  
ENA — Amplitude Modulation Data  
Input Enable  
When ENA is HIGH, AM is latched  
into the input register on the rising  
edge of clock. When ENA is LOW, the  
value stored in the register is un-  
changed.  
*TRANSFORM  
PROCESSOR  
OBIQ  
16  
16  
16  
16  
ENP1-0 — Phase Modulation Data Input  
Control  
OEI  
OEQ  
ENP1-0 is the 2-bit Phase Modulation  
Data Input Control that determines  
one of the four modes shown in Table  
1. ‘M’ is the Modulation Register and  
‘C’ is the Carrier Register as shown in  
the Functional Block Diagram.  
I
15-0  
Q
15-0  
*REQUIRES 18 CYCLES TO COMPLETE AND IS FULLY PIPELINED  
SIGNAL DEFINITIONS  
Power  
Inputs  
AM14-0 — Amplitude Modulation Data  
Input  
TABLE 1. REGISTER OPERATION  
Vcc and GND  
ENP1-0 Configuration  
AM14-0 is the 15-bit Amplitude  
Modulation Data input port. AM14-0  
is latched on the rising edge of CLK.  
+5V power supply. All pins must be  
connected.  
0 0  
0 1  
1 0  
1 1  
No registers enabled, current data held  
M register input enabled, C data held  
C register input enabled, M data held  
M register = 0, C register input enabled  
Clock  
PH31-0 — Phase Angle Data Input  
CLK — Master Clock  
PH31-0 is the 32-bit Phase Angle Data  
input port. Input phase accumulators  
are loaded through this port into  
registers enabled by ENP1-0. PH31-0 is  
latched on the rising edge of CLK.  
The rising edge of CLK strobes all  
enabled registers.  
TABLE 2. ACCUMULATOR CONTROL  
FM PM Configuration  
0
0
1
1
0
1
0
1
No accumulation (normal operation)  
PM accumulator path enabled  
FM accumulator path enabled  
Logical OR of PM and FM (Nonsensical)  
Special Arithmetic Functions  
08/16/2000–LDS.2340-E  
2