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L2340QC20 参数 Datasheet PDF下载

L2340QC20图片预览
型号: L2340QC20
PDF下载: 下载PDF文件 查看货源
内容描述: 数字频率合成器 [Digital Synthesizer]
分类和应用:
文件页数/大小: 11 页 / 270 K
品牌: LOGIC [ LOGIC DEVICES INCORPORATED ]
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L2340  
DEVICES INCORPORATED  
Digital Synthesizer  
NOTES  
1. Maximum Ratings indicate stress 9. AC specifications are tested with  
11. For the tENA test, the transition is  
specifications only. Functional oper- input transition times less than 3 ns, measured to the 1.5 V crossing point  
ation of these products at values be- output reference levels of 1.5 V (except  
yond those indicated in the Operating  
with datasheet loads. For the tDIS test,  
the transition is measured to the  
tDIS test), and input levels of nominally  
Conditions table is not implied. Expo- 0 to 3.0 V. Output loading may be a ±200mV level from the measured  
sure to maximum rating conditions for resistive divider which provides for steady-state output voltage with  
extended periods may affect reliability.  
±10mA loads. The balancing volt-  
age, VTH, is set at 3.5 V for Z-to-0  
specified IOH and IOL at an output  
voltage of VOH min and VOL max  
2. The products described by this spec-  
ification include internal circuitry de-  
signedto protect the chipfrom damag-  
ing substrate injection currents and ac-  
cumulations of static charge. Never-  
theless, conventional precautions  
should be observed during storage,  
handling, and use of these circuits in This device has high-speed outputs ca-  
order to avoid exposure to excessive pable of large instantaneous current  
respectively. Alternatively, a diode and 0-to-Z tests, and set at 0 V for Z-  
bridge with upper and lower current to-1 and 1-to-Z tests.  
sources of IOH and IOL respectively,  
12. These parameters are only tested at  
and a balancing voltage of 1.5 V may be  
the high temperature extreme, which is  
used. Parasitic capacitance is 30 pF  
the worst case for leakage current.  
minimum, and may be distributed.  
FIGURE A. OUTPUT LOADING CIRCUIT  
electrical stress values.  
pulses and fast turn-on/turn-off times.  
Asaresult, caremustbeexercisedinthe  
testing of this device. The following  
measures are recommended:  
S1  
DUT  
3. This device provides hard clamping  
of transient undershoot and overshoot.  
Input levels below ground or above  
VCC will be clamped beginning at –  
I
OL  
V
TH  
CL  
I
OH  
a. A 0.1 µF ceramic capacitor should be  
0.6 V and VCC + 0.6 V. The device can installed between VCC and Ground  
withstand indefinite operation with in- leads as close to the Device Under Test  
puts in the range of –0.5 V to +7.0 V. (DUT) as possible. Similar capacitors  
FIGURE B. THRESHOLD LEVELS  
t
ENA  
tDIS  
Device operation will not be adversely  
affected, however, input current levels and the tester common, and device  
should be installed between device VCC  
OE  
0
1.5 V  
1.5 V  
will be well in excess of 100 mA.  
ground and tester common.  
Z
Z
3.5V Vth  
1.5 V  
1.5 V  
V
OL*  
0.2 V  
0.2 V  
0
1
Z
Z
4. Actual test conditions may vary  
b. Ground and VCC supply planes  
from those designated but operation is must be brought directly to the DUT  
guaranteed as specified. socket or contactor fingers.  
V
OH*  
1
0V Vth  
VOL*  
Measured VOL with IOH = –10mA and IOL = 10mA  
V
OH* Measured VOH with IOH = –10mA and IOL = 10mA  
5. Supplycurrentforagivenapplication c. Input voltages should be adjusted to  
can be accurately approximated by:  
compensateforinductivegroundand VCC  
noise to maintain required DUT input  
levels relative to the DUT ground pin.  
2
NCV F  
4
where  
10. Each parameter is shown as a min-  
imum or maximum value. Input re-  
quirements are specified from the point  
of view of the external system driving  
the chip. Setup time, for example, is  
specified as a minimum since the exter-  
nal system must supply at least that  
much time to meet the worst-case re-  
quirementsofallparts. Responsesfrom  
the internal circuitry are specified from  
the point of view of the device. Output  
delay, for example, is specified as a  
maximumsinceworst-caseoperationof  
anydevicealwaysprovidesdatawithin  
that time.  
N = total number of device outputs  
C = capacitive load per output  
V = supply voltage  
F = clock frequency  
6. Tested with all outputs changing ev-  
ery cycle and no load, at a 20 MHz clock  
rate.  
7. Tested with all inputs within 0.1 V of  
VCC or Ground, no load.  
8. These parameters are guaranteed  
but not 100% tested.  
Special Arithmetic Functions  
08/16/2000–LDS.2340-E  
9