Application Support Information
The Application Engineering Group is available to assist you with the application design associated with ASDL-7021
FIR/VFIR Controller. You can contact them through your local sales representatives for additional details.
Order Information
Part Number
ASDL-70
Packaging Type
Tape and Reel
Quantity
4000
I/O Pins Configuration Table
Pins Description
Symbol
Power
VDDK
VDDC
VIO
VIO
VIO
GND
C4,C5,C6
C
E4,F5
D6
B
A,B,C,D,E
POWER
POWER
POWER
POWER
POWER
POWER
.8V Power
.V Power
.8V, .5V, .V
.8V, .5V, .V
.8V, .5V, .V
GND
Pin(s)
Type
Buffer Type
(Refer to Figure 2)
Description
Bus Interface Signals (VIO1 Voltage)
A0-A7
D,D,E,E,
G,G,F,F
G,F,F4,G4
G5,F7,G6,G7
F6
E5
I
I
An 8-bit address signal line connects itself directly with an external address bus. It selects the
internal buffer memory and the register addresses of each function module. With the assertion
of the CS signal, A0 - A7 turn out to be valid, which decides the internal addresses.
An 8-bit data signal line connects itself directly with an external data bus. It is a signal that
performs data conversion with the internal buffer memory and each function module.The bus
direction is determined by WE and OE.
CS is a chip select signal for the IC. Asserting CS activates the external bus of this LSI.
The WE signal turns the direction of a data bus to the input direction, and takes it into the IC for
the internal buffer memory and registers designated by the address bus, at the start-up of the
signal.
The OE signal turns the data bus direction to the output direction, and outputs to the data bus
the contents of the internal buffer memory and register designated by the address bus.
This is a signal line that notifies to the outside that ASDL-70 requests an interrupt.
D0-D7
I/O
IO4
/CS
/WE
I
I
I
I
/OE
/IRQ
E6
D7
I
O
I
O4
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