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LTC2487IDEPBF 参数 Datasheet PDF下载

LTC2487IDEPBF图片预览
型号: LTC2487IDEPBF
PDF下载: 下载PDF文件 查看货源
内容描述: 16位双/四通道ADC与PGA ,易于驱动和I2C接口 [16-Bit 2-/4-Channel ADC with PGA, Easy Drive and I2C Interface]
分类和应用: 驱动
文件页数/大小: 32 页 / 651 K
品牌: Linear [ Linear ]
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LTC2487  
applicaTions inForMaTion  
the input channel. The second word of data (IM, FA, FB,  
SPD, GS2, GS1, GS0) is used to select the frequency  
rejection, speed mode (1x, 2x), temperature measure-  
ment, and gain.  
If the first three bits shifted into the device are 101, then  
the next five bits select the input channel for the next  
conversion cycle (see Table 3).  
Table 3 Channel Selection  
MUX ADDRESS  
ODD/  
SGL SIGN A2  
CHANNEL SELECTION  
After power-up, the device initiates an internal reset cycle  
+
whichsetstheinputchanneltoCH0-CH1(IN =CH0, IN =  
CH1),thefrequencyrejectiontosimultaneous50Hz/60Hz,  
and1xoutputrate(auto-calibrationenabled),andgain=1.  
Therstconversionautomaticallybeginsatpower-upusing  
thisdefaultconfiguration.Oncetheconversioniscomplete,  
up to two words may be written into the device.  
A1  
0
A0  
0
0
1
2
IN  
IN  
IN  
3
IN  
IN  
COM  
+
+
*0  
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
IN  
IN  
+
+
+
0
1
+
0
0
0
IN  
IN  
IN  
IN  
0
0
1
1
0
0
IN  
The first three bits of the first input word consist of two  
preamble bits and one enable bit. Valid settings for these  
three bits are 000, 100, and 101. Other combinations  
should be avoided.  
1
0
1
IN  
+
1
0
0
IN  
+
1
0
1
IN  
IN  
*Default at power up  
If the first three bits are 000 or 100, the following data is ig-  
nored(don’tcare)andthepreviouslyselectedinputchannel  
and configuration remain valid for the next conversion.  
The first input bit (SGL) following the 101 sequence de-  
termines if the input selection is differential (SGL = 0) or  
single-ended(SGL=1).ForSGL=0,twoadjacentchannels  
1
7
8
9
1
2
9
1
2
3
4
5
6
7
8
9
SCL  
SDA  
7-BIT  
ADDRESS  
R
SIG  
MSB  
D23  
LSB  
ACK BY  
LTC2487  
ACK BY  
MASTER  
NAK BY  
MASTER  
START BY  
MASTER  
ALWAYS LOW  
2487 F03a  
SLEEP  
DATA OUTPUT  
Figure 3a. Timing Diagram for Reading from the LTC2487  
1
2
7
8
9
1
9
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
9
SCL  
SDA  
1
0
EN  
SGL ODD  
A2  
A1 A0  
EN2 IM  
FA FB SPD GS2 GS1 GS0  
W
7-BIT ADDRESS  
ACK BY  
LTC2487  
ACK BY  
LTC2487  
(OPTIONAL 2ND BYTE)  
ACK BY  
LTC2487  
START BY  
MASTER  
2487 F03b  
SLEEP  
DATA INPUT  
Figure 3b. Timing Diagram for Writing to the LTC2487  
2487fa  
ꢀꢅ  
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