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LT3580IDD-PBF 参数 Datasheet PDF下载

LT3580IDD-PBF图片预览
型号: LT3580IDD-PBF
PDF下载: 下载PDF文件 查看货源
内容描述: 升压/负输出DC / DC转换器,具有2A开关,软起动和同步 [Boost/Inverting DC/DC Converter with 2A Switch, Soft-Start, and Synchronization]
分类和应用: 转换器开关
文件页数/大小: 28 页 / 458 K
品牌: LINER [ LINEAR TECHNOLOGY ]
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LT3580
APPLICATIONS INFORMATION
for boost, coupled inductor SEPIC and coupled inductor
inverting topologies, or:
L1 L2
>
2(f) I
LIM
DC • V
IN
V
OUT
• I
OUT
V
IN
thus causing duty cycle jitter and/or poor regulation. The
maximum inductance can be calculated by:
L
MAX
=
I
OUT
V
IN
– V
CESAT
DC
I
MIN RIPPLE
f
for the uncoupled inductor SEPIC and uncoupled inductor
inverting topologies.
where:
DC = switch duty cycle (see previous section)
I
LIM
= switch current limit, typically about 2.4A at 50%
duty cycle (see the Typical Performance Characteristics
section).
η
= power conversion efficiency (typically 88% for
boost and 75% for dual inductor topologies at high
currents).
f = switching frequency
Negative values of L
MIN1
indicate that the output load
current I
OUT
exceeds the switch current limit capability
of the LT3580.
where L
MAX
is L1||L2 for dual inductor topologies and a
good choice for I
MIN-RIPPLE
is 300mA.
Current Rating:
Finally, the inductor(s) must have a rating
greater than its peak operating current to prevent inductor
saturation resulting in efficiency loss. In steady state, the
peak input inductor current (continuous conduction mode
only) is given by:
I
L1
PEAK
=
V
OUT
•I
OUT
V
IN
+
V
IN
• DC
2 • L1• f
for the boost, uncoupled inductor SEPIC and uncoupled
inductor inverting topologies, or:
I
L1
PEAK
| V
OUT
•I
OUT
| V
IN
• DC
+
V
IN
• • DC 2 • L1• f
for the coupled inductor SEPIC and coupled inductor
inverting topology.
For dual inductor topologies, the peak output inductor
current is given by:
I
L2
PEAK
=I
OUT
+
Avoiding Subharmonic Oscillations:
The LT3580’s internal
slope compensation circuit will prevent subharmonic oscil-
lations that can occur when the duty cycle is greater than
50%, provided that the inductance exceeds a minimum
value. In applications that operate with duty cycles greater
than 50%, the inductance must be at least:
V •
(
2 • DC – 1
)
L
>
IN
(1 DC) • (f) • 0.8
for boost, coupled inductor SEPIC, and coupled inductor
inverting topologies, or:
V •
(
2 • DC – 1
)
L1 L2
>
IN
(1 DC) • (f) • 0.8
for the uncoupled inductor SEPIC and uncoupled inductor
inverting topologies.
V
OUT
(
1– DC
)
2 • L2 • f
for the uncoupled inductor topologies, or
I
L2
PEAK
V
OUT
(
1– DC
)
I
OUT
+
1– DC
2 • L2 • f
for the coupled inductor topologies
Capacitor Selection
Low ESR (equivalent series resistance) capacitors should
be used at the output to minimize the output ripple voltage.
Multilayer ceramic capacitors are an excellent choice, as
they have an extremely low ESR and are available in very
small packages. X5R or X7R dielectrics are preferred, as
these materials retain their capacitance over wider voltage
3580fc
Maximum Inductance:
Excessive inductance can reduce
current ripple to levels that are difficult for the current com-
parator (A3 in the Block Diagram) to cleanly discriminate,
10