LT1940/LT1940L
U
W U U
APPLICATIO S I FOR ATIO
RUN/SS1
V
C2
RUN/SS1
OFF ON
1nF
1nF
OFF ON
RUN/SS2
GND
PG1
RUN/SS2
GND
2.2nF
(5a) Channel 2 is Delayed
(5b) Fewest Components
RUN/SS1
RUN/SS1
OFF ON
OFF ON
1nF
1nF
PG1
PG1
RUN/SS2
RUN/SS2
GND
GND
OFF2 ON2
1.5nF
1.5nF
1940 F05
(5c) Independent Control of Channel 2
(5d) Doesn't Work !
Figure 5. Several Methods of Sequencing the Two Outputs. Channel 1 Starts First.
PARASITIC DIODE
D4
V
IN
SW
V
IN
V
OUT
LT1940
1940 F06
Figure 6. Diode D4 Prevents a Shorted Input from Discharging a Backup Battery Tied to the Output.
Shorted Input Protection
PCB Layout
If the inductor is chosen so that it won’t saturate exces-
sively, the LT1940 will tolerate a shorted output. There is
another situation to consider in systems where the output
will be held high when the input to the LT1940 is absent.
If the VIN and one of the RUN/SS pins are allowed to float,
then the LT1940’s internal circuitry will pull its quiescent
current through its SW pin. This is fine if your system can
tolerate a few mA of load in this state. With both RUN/SS
pins grounded, the LT1940 enters shutdown mode and
the SW pin current drops to ~30µA. However, if the VIN pin
is grounded while the output is held high, then parasitic
diodes inside the LT1940 can pull large currents from the
output through the SW pin and the VIN pin. A Schottky
diode in series with the input to the LT1940 will protect the
LT1940 and the system from a shorted or reversed input.
For proper operation and minimum EMI, care must be
taken during printed circuit board (PCB) layout. Figure 7
shows the high-di/dt paths in the buck regulator circuit.
Note that large, switched currents flow in the power
switch, the catch diode and the input capacitor. The loop
formed by these components should be as small as
possible. These components, along with the inductor and
output capacitor, should be placed on the same side of the
circuit board, and their connections should be made on
that layer. Place a local, unbroken ground plane below
these components, and tie this ground plane to system
groundatonelocation,ideallyatthegroundterminalofthe
output capacitor C2. Additionally, the SW and BOOST
nodes should be kept as small as possible. Figure 8 shows
recommended component placement with trace and via
locations.
1940fa
14
Linear [ Linear ]
