LT1507
U
W U U
APPLICATIONS INFORMATION
2.0
1.5
1.0
0.5
0
80
Example: with VIN = 5V, VOUT = 3.3V, IOUT = 1A;
GAIN (A/V)
2
40
(0.4)(1) (3.3)
5
−9
3
P
=
+ 16 10
1 5 500 10
( )( )
SW
(
)
(
)
0
= 0.26 + 0.04 = 0.3W
PHASE
2
1
(3.3)
P
=
0.008
0.046W
+
=
BOOST
V
= 3.3V
–40
–80
OUT
OUT
IN
75
5
I
= 250mA
V
= 5V
L = 10µH
P = 5(0.003)+ 3.3(0.005) = 0.032W
Q
10
100
1k
10k
100k
FREQUENCY (Hz)
Total power dissipation is 0.3 + 0.046 + 0.032 = 0.38W.
LT1507 • F08
Thermal resistance for the LT1507 packages is influenced
by the presence of internal or backside planes. With a full
plane under the SO package, thermal resistance will be
about120°C/W. Noplanewillincreaseresistancetoabout
150°C/W. To calculate die temperature, use the proper
thermal resistance number for the desired package and
add in worst-case ambient temperature;
Figure 8. Phase and Gain from VC Pin Voltage
to Inductor Current
parallel with 12pF. In all practical applications, the com-
pensation network from VC pin to ground has a much
lower impedance than the output impedance of the ampli-
fier at frequencies above 500Hz. This means that the error
amplifier characteristics themselves do not contribute
excess phase shift to the loop and the phase/gain charac-
teristics of the error amplifier section are completely
controlled by the external compensation network.
TJ = TA + θJA(PTOT
)
With the S8 package (θJA = 120°C/W) at an ambient
temperature of 70°C;
TJ = 70 + 120(0.38) = 116°C
The complete small-signal model is shown in Figure 9. R1
andR2arethedividerusedtosetoutputvoltage.Theseare
internal on the fixed voltage LT1507-3.3 with R1 = 1.8k
and R2 = 5k. RC, CC and CF are external compensation
FREQUENCY COMPENSATION
The LT1507 uses a “current mode” architecture to help
alleviate phase shift created by the inductor. The basic
connectionsareshowninFigure9.Gainofthepowerstage
can be modeled as 1.8A/V transconductance from the VC
pin voltage to current delivered to the output. This is
shown in Figure 8 where the transconductance from VC
pin to inductor current is essentially flat from 50Hz to
50kHz and phase shift is minimal in the important loop
unity-gain band of 1kHz to 50kHz. Inductor variation from
3µH to 20µH will have very little effect on these curves.
V
SW
L1
LT1507
POWER STAGE
= 1.8A/V
OUTPUT
g
m
ERROR AMPLIFIER
= 2000µho
R1
R2
12pF
200k
g
m
F
B
–
ESR
+
+
2.42V
C1
GND
V
C
Overall gain from the VC pin to output is then modeled as
the product of 1.8A/V transconductance multiplied by the
complex impedance of the load in parallel with the output
capacitor model.
R
C
C
F
C
C
1507 • F09
The error amplifier can be modeled as a transconductance
of 2000µmho, with an output impedance of 200kΩ in
Figure 9. Small-Signal Model for Loop Stability Analysis
18
Linear [ Linear ]
