LT3472
APPLICATIO S I FOR ATIO
the sum of the two outputs is always positive. The se-
quencing is shown in Figure 6.
Board Layout Consideration
As with all switching regulators, careful attention must be
paid to the PCB board layout and component placement.
To maximize efficiency, switch rise and fall times are made
as short as possible. To prevent electromagnetic interfer-
V
POS
5V/DIV
V
NEG
5V/DIV
V
SHDN
5V/DIV
100µs/DIV
3472 FO6
Figure 6. Start-Up Sequencing
U
ence (EMI) problems, proper layout of the high frequency
switching path is essential. The voltage signals of the SWP
and SWN pins have rise and fall times of a few ns. Minimize
the length and area of all traces connected to the SWP and
SWN pins and always use a ground plane under the
switching regulator to minimize interplane coupling. Rec-
ommended component placement is shown in Figure 7.
C
OP
C
IN
L
P
R
FBP
L
N1
C
FBP
C
SSP
C
NF
L
N2
C
ON
R
FBN
C
FBN
C
SSN
3472 F06
W
U U
Figure 7. Recommended Component Placement
3472f
9
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