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1977EFE 参数 Datasheet PDF下载

1977EFE图片预览
型号: 1977EFE
PDF下载: 下载PDF文件 查看货源
内容描述: 高电压1.5A , 500kHz的降压型开关稳压器具有100uA的静态电流 [High Voltage 1.5A, 500kHz Step-Down Switching Regulator with 100uA Quiescent Current]
分类和应用: 稳压器开关
文件页数/大小: 24 页 / 274 K
品牌: LINER [ LINEAR TECHNOLOGY ]
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LT1977
TYPICAL PERFOR A CE CHARACTERISTICS
Burst Mode Operation
Burst Mode Operation
V
OUT
20mV/DIV
I
SW
500mA/DIV
V
IN
= 12V
V
OUT
= 3.3V
I
Q
= 100µA
No Load 1A Step Response
V
OUT
50mV/DIV
I
OUT
500mA/DIV
V
IN
= 12V
V
OUT
= 3.3V
C
OUT
= 100µF
I
DC
= 0mA
PI FU CTIO S
NC (Pins 1, 3, 5):
No Connection.
SW (Pin 2):
The SW pin is the emitter of the on-chip power
NPN switch. This pin is driven up to the input pin voltage
during switch on time. Inductor current drives the SW pin
negative during switch off time. Negative voltage is clamped
with the external catch diode. Maximum negative switch
voltage allowed is –0.8V.
V
IN
(Pin 4):
This is the collector of the on-chip power NPN
switch. V
IN
powers the internal control circuitry when a
voltage on the BIAS pin is not present. High di/dt edges
occur on this pin during switch turn on and off. Keep the
path short from the V
IN
pin through the input bypass
capacitor, through the catch diode back to SW. All trace
inductance on this path will create a voltage spike at switch
off, adding to the V
CE
voltage across the internal NPN.
BOOST (Pin 6):
The BOOST pin is used to provide a drive
voltage, higher than the input voltage, to the internal
bipolar NPN power switch. Without this added voltage, the
typical switch voltage loss would be about 1.5V. The
additional BOOST voltage allows the switch to saturate
and its voltage loss approximates that of a 0.2Ω FET
structure.
C
T
(Pin 7):
A capacitor on the C
T
pin determines the amount
of delay time between the PGFB pin exceeding its thresh-
old (V
PGFB
) and the PG pin set to a high impedance state.
When the PGFB pin rises above V
PGFB
, current is sourced
from the C
T
pin into the external capacitor. When the volt-
age on the external capacitor reaches an internal clamp
(V
CT
), the PG pin becomes a high impedance node. The
resultant PG delay time is given by t = C
CT
• V
CT
/I
CT
. If the
1977f
6
U W
V
OUT
20mV/DIV
I
SW
500mA/DIV
5ms/DIV
1977 G14
V
IN
= 12V
V
OUT
= 3.3V
I
Q
= 100µA
2µs/DIV
1977 G15
Step Response
V
OUT
50mV/DIV
I
OUT
500mA/DIV
500µs/DIV
1977 G17
V
IN
= 12V
V
OUT
= 3.3V
C
OUT
= 100µF
I
DC
= 350mA
500µs/DIV
1977 G18
U
U
U