LT1977
The
●
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
J
= 25°C. V
IN
= 12V, SHDN = 12V, BIAS = 5V, FB/PGFB = 1.25V, C
SS
/SYNC = 0V
unless otherwise noted.
SYMBOL
PARAMETER
Switch On Resistance (Note 9)
Switching Frequency
Maximum Duty Cycle
Minimum SYNC Amplitude
SYNC Frequency Range
SYNC Input Impedance
I
CSS
I
PGFB
V
PGFB
I
CT
V
CT
C
SS
Current Threshold (Note 10)
PGFB Input Current
PGFB Voltage Threshold (Note 11)
C
T
Source Current (Note 11)
C
T
Sink Current (Note 11)
C
T
Voltage Threshold (Note 11)
PG Leakage (Note 11)
PG Sink Current (Note 11)
V
PG
= 12V
PGFB = 1V, PG = 400mV
100
●
ELECTRICAL CHARACTERISTICS
CONDITIONS
●
●
MIN
425
86
575
7
88
2
1
1.16
TYP
0.2
500
92
1.5
700
85
13
25
90
3.6
2
1.2
0.1
200
MAX
0.4
575
2.0
UNITS
Ω
kHz
%
V
kHz
kΩ
20
100
92
5.5
1.26
1
µA
nA
%
µA
mA
V
µA
µA
Note 1:
Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2:
The LT1977EFE is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C to
125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT1977IFE is guaranteed and tested over the full –40°C to 125°C
operating junction temperature range.
Note 3:
Minimum input voltage is defined as the voltage where switching
starts. Actual minimum input voltage to maintain a regulated output will
depend upon output voltage and load current. See Applications
Information.
Note 4:
Supply input current is the quiescent current drawn by the input
pin. Its typical value depends on the voltage on the BIAS pin and operating
state of the LT1977. With the BIAS pin at 0V, all of the quiescent current
required to operate the LT1977 will be provided by the V
IN
pin. With the
BIAS voltage above its minimum input voltage, a portion of the total
quiescent current will be supplied by the BIAS pin. Supply sleep current is
defined as the quiescent current during the “sleep” portion of Burst Mode
operation. See Applications Information for determining application supply
currents.
Note 5:
Minimum BIAS voltage is the voltage on the BIAS pin when I
BIAS
is
sourced into the pin.
Note 6:
This is the minimum voltage across the boost capacitor needed to
guarantee full saturation of the internal power switch.
Note 7:
Boost current is the current flowing into the BOOST pin with the pin
held 3.3V above input voltage. It flows only during switch on time.
Note 8:
Gain is measured with a V
C
swing from 1.15V to 750mV.
Note 9:
Switch on resistance is calculated by dividing V
IN
to SW voltage by the
forced current (1.5A). See Typical Performance Characteristics for the graph
of switch voltage at other currents.
Note 10:
The C
SS
threshold is defined as the value of current sourced into the
C
SS
pin which results in an increase in sink current from the V
C
pin. See the
Soft-Start section in Applications Information.
Note 11:
The PGFB threshold is defined as the percentage of V
REF
voltage
which causes the current source output of the C
T
pin to change from
sinking (below threshold) to sourcing current (above threshold). When
sourcing current, the voltage on the C
T
pin rises until it is clamped
internally. When the clamp is activated, the output of the PG pin will be set
to a high impedance state. When the C
T
clamp is inactive the PG pin will
be set active low with a current sink capability of 200µA.
1977f
3
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