LTC1735
U
W U U
APPLICATIO S I FOR ATIO
FCB Pin Operation
include this current when choosing resistor values R3
and R4.
WhentheFCBpindropsbelowits0.8Vthreshold,continu-
ous mode operation is forced. In this case, the top and
bottom MOSFETs continue to be driven synchronously
regardless of the load on the main output. Burst Mode
operation is disabled and current reversal is allowed in the
inductor.
The internal LTC1735 oscillator can be synchronized to an
external oscillator by applying and clocking the FCB pin
with a signal above 1.5VP–P. When synchronized to an
external frequency, Burst Mode operation is disabled but
cycleskippingisallowedatlowloadcurrentssincecurrent
reversal is inhibited. The bottom gate will come on every
10 clock cycles to assure the bootstrap cap is kept re-
freshed. The rising edge of an external clock applied to the
FCB pin starts a new cycle. The FCB pin must not be driven
when the device is in shutdown (RUN/SS pin low).
In addition to providing a logic input to force continuous
synchronous operation and external synchronization, the
FCB pin provides a means to regulate a flyback winding
output (refer to Figure 3a). During continuous mode,
current flows continuously in the transformer primary.
The secondary winding(s) draw current only when the
bottom, synchronous switch is on. When primary load
currents are low and/or the VIN/VOUT ratio is low, the
synchronous switch may not be on for a sufficient amount
of time to transfer power from the output capacitor to the
secondary load. Forced continuous operation will support
secondary windings provided there is sufficient synchro-
nous switch duty factor. Thus, the FCB input pin removes
the requirement that power must be drawn from the
inductor primary in order to extract power from the
auxiliary windings. With the loop in continuous mode, the
auxiliary outputs may nominally be loaded without regard
to the primary output load.
The range of synchronization is from 0.9fO to 1.3fO, with
fO set by COSC. Attempting to synchronize to a higher
frequency than 1.3fO can result in inadequate slope com-
pensation and cause loop instability with high duty cycles
(duty cycle > 50%). If loop instability is observed while
synchronized, additional slope compensation can be ob-
tained by simply decreasing COSC
.
The following table summarizes the possible states avail-
able on the FCB pin:
Table 1
FCB Pin
Condition
DC Voltage: 0V to 0.7V
Burst Disabled/Forced Continuous
Current Reversal Enabled
The secondary output voltage VSEC is normally set as
shown in Figure 3a by the turns ratio N of the transformer:
DC Voltage: ≥ 0.9V
Burst Mode Operation,
No Current Reversal
Feedback Resistors
Regulating a Secondary Winding
VSEC (N + 1)VOUT
Ext Clock: (0V to V
)
Burst Mode Operation Disabled
No Current Reversal
FCBSYNC
However, if the controller goes into Burst Mode operation
and halts switching due to a light primary load current,
then VSEC will droop. An external resistive divider from
(V
FCBSYNC
> 1.5V)
Efficiency Considerations
VSEC to the FCB pin sets a minimum voltage VSEC(MIN)
:
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:
R4
R3
V
≈ 0.8V 1+
SEC(MIN)
If VSEC drops below this level, the FCB voltage forces
continuous switching operation until VSEC is again above
its minimum.
%Efficiency = 100% – (L1 + L2 + L3 + …)
whereL1, L2, etc. aretheindividuallossesasapercentage
of input power.
Inordertopreventerraticoperationifnoexternalconnec-
tions are made to the FCB pin, the FCB pin has a 0.17µA
internalcurrentsourcepullingthepinhigh. Rememberto
1735fc
20
Linear [ Linear ]
