LT1469
APPLICATIONS INFORMATION
Capacitive Loading
measurements—ApplicationNotes47and74.AppendixB
of AN47 is a vital primer on 12-bit settling measurements
andAN74extendsthestate-of-the-artwhileconcentrating
on settling time with a 16-bit current output DAC input.
TheLT1469drivescapacitiveloadsofupto100pFinunity-
gain and 300pF in a gain of –1. When there is a need to
drivealargercapacitiveload,asmallseriesresistorshould
be inserted between the output and the load. In addition,
a capacitor should be added between the output and the
inverting input as shown in Figure 3.
The settling of the DAC I-to-V converter on the front page
was measured using the exact methods of AN74. The
optimum nulling of the DAC output capacitance requires
15pFacrossthe12kfeedbackresistor.Thetheoreticallimit
for 16-bit settling is 11.1 times this RC time constant or
2μs. The actual settling time is 2.4μs at the output of the
LT1469.
Settling Time
The LT1469 is a single stage amplifier with an optimal
thermal layout that leads to outstanding settling per-
formance. Measuring settling even at the 12-bit level is
very challenging, and at the 16-bit level requires a great
deal of subtlety and expertise. Fortunately, there are two
excellent Linear Technology reference sources for settling
The RC output noise filter adds a slight settling time delay
butreducesthenoisebandwidthto1.6MHzwhichincreases
the output resolution for 16-bit accuracy.
R
F
R
F
≥ (1 + R /R )/(2Č • C • 5MHz)
F G L
O
R ≥ 10R
O
C = (2R /R )C
F
O
F
L
C
R
F
G
–
R
O
1/2 LT1469
V
OUT
C
L
V
IN
+
1469 F03
Figure 3. Driving Capacitive Loads
1469fa
13
Linear [ Linear ]
