LT1469-2
APPLICATIONS INFORMATION
Input Considerations
The input bias currents vary with common mode voltage.
The cancellation circuitry was not designed to track this
common mode voltage because the settling time would
have been adversely affected.
Each input of the LT1469 is protected with a 100Ω series
resistor and back-to-back diodes across the bases of
the input devices. If large differential input voltages are
anticipated, limit the input current to less than 10mA with
an external series resistor. Each input also has two ESD
clamp diodes—one to each supply. If an input is driven
beyond the supply, limit the current with an external resis-
tor to less than 10mA.
The LT1469 inputs can be driven to the negative supply
and to within 0.±5 of the positive supply without phase
reversal. As the input moves closer than 0.±5 to the posi-
tive supply, the output reverses phase.
Total Input Noise
TheLT1469employsbiascurrentcancellationattheinputs.
The inverting input current is trimmed at zero common
mode voltage to minimize errors in inverting applications
such as I-to-5 converters. The noninverting input current
is not trimmed and has a wider variation and therefore a
larger maximum value. As the input offset current can be
greaterthaneitherinputcurrent,theuseofbalancedsource
resistance is NOT recommended as it actually degrades
DC accuracy and also increases noise.
ThetotalinputnoiseoftheLT1469isoptimizedforasource
resistance between 1k and 20k. Within this range, the
total input noise is dominated by the noise of the source
resistance itself. When the source resistance is below
1k, voltage noise of the amplifier dominates. When the
source resistance is above 20k, the input noise current is
the dominant contributor.
SIMPLIFIED SCHEMATIC
+
5
I1
I2
I±
Q10
Qꢂ
Q9
OUT
+IN
Q1
Q2
ꢀIN Q±
Q3
Q6
Q7
Q11
Q4
C
BIAS
I3
I4
I6
ꢀ
5
14692 SS
14692f
10
Linear [ Linear ]
