LTC1446/LTC1446L
U
OPERATIO
Voltage Output
Serial Interface
The LTC1446/LTC1446L include an internal voltage refer-
ence which is connected to each DAC. The LTC1446 has a
full scale of 4.095V making 1LSB equal to 1mV. The
LTC1446L has a full scale of 2.5V making 1LSB equal to
0.61mV.
The data on the DIN input is loaded into the shift register
on the rising edge of the clock. Data is loaded as one 24-
bit word where the first 12 bits are for DAC A and the
second12areforDACB.Foreach12-bitsegmenttheMSB
isloadedfirst.Datafromtheshiftregisterisloadedintothe
DAC register when CS/LD is pulled high. The clock is
disabledinternallywhenCS/LDishigh. Note:CLKmustbe
low before CS/LD is pulled low to avoid an extra internal
clock pulse.
The LTC1446/LTC1446L rail-to-rail buffered outputs can
source or sink 5mA when operating with a 5V supply while
pulling to within 300mV of the positive supply voltage or
ground. The outputs swing to within a few millivolts of
either supply rail when unloaded and have an equivalent
output resistance of 40Ω when driving a load to the rails.
The buffer amplifiers can drive 1000pF without going into
oscillation. The output noise spectral density is
600nV/√Hz at 1kHz.
The buffered output of the 24-bit shift register is available
on the DOUT pin which swings from GND to VCC.
Multiple LTC1446/LTC1446L’s may be daisy-chained to-
getherbyconnectingtheDOUT pintotheDIN pinofthenext
chip, while the clock and CS/LD signals remain common
to all chips in the daisy chain. The serial data is clocked to
all of the chips, then the CS/LD signal is pulled high to
update all of them simultaneously.
8
Linear [ Linear ]
