LTC1408-12
6 Channel, 12-Bit, 600ksps
Simultaneous Sampling ADC
with Shutdown
DESCRIPTIO
The LTC
®
1408-12 is a 12-bit, 600ksps ADC with six
simultaneously sampled differential inputs. The device
draws only 5mA from a single 3V supply, and comes in a
tiny 32 pin (5mm
×
5mm) QFN package. A SLEEP shut-
down feature further reduces power consumption to
6µW. The combination of low power and tiny package
makes the LTC1408-12 suitable for portable applications.
The LTC1408-12 contains six separate differential inputs
that are sampled simultaneously on the rising edge of the
CONV signal. These six sampled inputs are then
converted at a rate of 100ksps per channel.
The 83dB common mode rejection allows users to
eliminate ground loops and common mode noise by
measuring signals differentially from the source.
The device converts 0V to 2.5V unipolar inputs differen-
tially, or
±1.25V
bipolar inputs also differentially,
depending on the state of the BIP pin. Any analog input
may swing rail-to-rail as long as the differential input
range is maintained.
The conversion sequence can be abbreviated to convert
fewer than six channels, depending on the logic state of
the SEL2, SEL1 and SEL0 inputs.
The serial interface sends out the six conversion results in
96 clocks for compatibility with standard serial interfaces.
FEATURES
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600ksps ADC with 6 Simultaneously Sampled
Differential Inputs
100ksps Throughput per Channel
72dB SINAD
Low Power Dissipation: 15mW
3V Single Supply Operation
2.5V Internal Bandgap Reference, Can be Overdriven
with External Reference
3-Wire SPI-Compatible Serial Interface
0V to 2.5V Unipolar, or
±1.25V
Bipolar Differential
Input Range
SLEEP (6µW) Shutdown Mode
NAP (3.3mW) Shutdown Mode
Internal Conversion Triggered by CONV
83dB Common Mode Rejection
Tiny 32-Pin (5mm
×
5mm) QFN Package
APPLICATIO S
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Multiphase Power Measurement
Multiphase Motor Control
Data Acquisition Systems
Uninterruptable Power Supplies
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents including 6084440, 6522187.
BLOCK DIAGRA
CH5
–
CH5
+
CH4
–
CH4
+
21
20
19
18
17
CH3
–
CH3
+
CH2
–
CH2
+
CH1
–
CH1
+
CH0
–
CH0
+
10µF
V
CC
16
15
14
12
13
11
10
9
8
7
6
5
4
24
–
–
S AND H
–
–
–
–
S AND H
S AND H
S AND H
S AND H
S AND H
600ksps
12-BIT ADC
MUX
TIMING
LOGIC
30
32
V
REF
10µF
23
29
BIP
26
27
28
235114 TA01
2.5V
REFERENCE
GND
33
22
U
W
U
3V
V
DD
25
12-BIT LATCH 0
12-BIT LATCH 1
12-BIT LATCH 2
12-BIT LATCH 3
12-BIT LATCH 4
12-BIT LATCH 5
OV
DD
3V
SD0
0.1µF
2
OGND
+
+
+
+
+
+
THREE-
STATE
SERIAL
OUTPUT
PORT
3
1
CONV
SCK
DGND
31
SEL2 SEL1 SEL0
140812f
1
LINER [ LINEAR TECHNOLOGY ]
