LTC1402
U
W U U
APPLICATIONS INFORMATION
HARDWARE INTERFACE TO TMS320C54x
edge clock. Buffers near the LTC1402 may be added to
drive long tracks to the DSP to prevent corruption of the
signal to LTC1402. This configuration is adequate to
traverseatypicalsystemboard,but sourceresistorsatthe
buffer outputs, and termination resistors at the DSP may
be needed to match the characteristic impedance of very
long transmission lines. If you need to terminate the DOUT
transmission line, buffer it first with one or two 74ACxx
gates. The TTL threshold inputs of the DSP port respond
properly to the 2.5V swing of the terminated transmission
lines.TheOVDD supplyoutputdriversupplyvoltagecanbe
driven directly from the DSP.
The LTC1402 is a serial output ADC whose interface has
been designed for high speed buffered serial ports in fast
digital signal processors (DSPs). Figure 14 shows an
example of this interface using a TMS320C54X.
The buffered serial port in the TMS320C54x has direct
accesstoa2kBsegmentofmemory. TheADC’sserialdata
can be collected in two alternating 1kB segments, in real
time, at the full 2.2Msps conversion rate of the LTC1402.
TheDSPassemblycodesetsframesyncmodeattheBFSR
pin to accept an external positive going pulse, and the
serial clock at the BCLKR pin to accept an external positive
5V
11
OV
DD
V
CC
16
15
CONV
LTC1402
SCK
BFSR
TMS320C54x
BCLKR
REF
B11 B10
10
9
D
BDR
OUT
OGND
CONV
CLK
3-WIRE SERIAL
INTERFACELINK
1402 F14
Figure 14. DSP Serial Interface to TMS320C54x
18
Linear [ Linear ]
