LTC1402
U
W U U
APPLICATIONS INFORMATION
edge of CONV. Please note the delay specification from speed crystal (i.e., 10MHz) to generated a fast, but jittery,
SCK to a valid DOUT. DOUT is always guaranteed to be valid phaselockedloopsystemclock(i.e., 40MHz). Thejitter, in
by the next rising edge of SCK.
these PLL-generated high speed clocks, can be several
nanoseconds. Note that if you choose to use the frame
syncsignalgeneratedbytheDSPport,thissignalwillhave
the same jitter of the DSP’s master clock.
DIGITAL JITTER AT CONV (PIN 16)
Inhighspeedapplications,wherehighamplitudesinewaves
above 100kHz are sampled, the CONV signal must have as
little jitter as possible (10ps or less). The square wave
SERIAL TO PARALLEL CONVERSION
output of a common crystal clock module usually meets YoucantakeadvantageoftheserialinterfaceoftheLTC1402
thisrequirementeasily.ThechallengeistogenerateaCONV in a parallel data system to minimize bus wiring conges-
signalfromthiscrystalclockwithoutjittercorruptionfrom tion in the PC board layout. Figure 13 shows an example
other digital circuits in the system. A clock divider and any of this interface. It is best to send the SCK and CONV
gates in the signal path from the crystal clock to the CONV signalstotheLTC1402,andthenbusthemtogetheracross
input should not share the same integrated circuit with the board to avoid excessive time skew among the three
other parts of the system. As shown in the interface circuit signals. It is usually not necessary to buffer DOUT, if the PC
examples, theLTC1402’sSCKandCONVinputsshouldbe track is not too long. Buffering SCK and CONV prevents
driven first with digital buffers used to drive the serial port jitter from corrupting these signals. The relative phase
interface. Also note that the master clock in the DSP may between SCK and CONV affects the position of the parallel
already be corrupted with jitter, even if it comes directly word at the output of the 74HC595. The position of the
from the DSP crystal. Another problem with high speed outputwordinFigure13assumes16clocksbetweeneach
processor clocks is that they often use a low cost, low CONV rising edge, and the CONV pulse is one clock wide.
5V
11
OV
DD
10
74ACT04
SRCLR
16
15
12
11
14
13
15
1
CONV
LTC1402
SCK
RCK
QA
QB
QC
QD
QE
D0
D1
D2
D3
D4
D5
D6
2
SRCK
3
74HC595
SER
10
9
4
D
OUT
5
QF
OGND
6
G
QG
QH
QH′
7
9
CONV
CLK
10
SRCLR
RCK
12
11
14
13
15
1
QA
QB
QC
QD
QE
D7
D8
2
SRCK
D9
3
74HC595
SER
D10
D11
REFRDY
3-WIRE SERIAL
INTERFACE LINK
4
5
QF
6
G
QG
QH
QH′
7
9
1402 F13
Figure 13. Serial to Parallel Interface
17
Linear [ Linear ]
