LTC1658
U
OPERATIO
Serial Interface
the chips then the CS/LD signal is pulled high to update all
of them simultaneously.
The data on the DIN input is loaded into the shift register
ontherisingedgeoftheclock.TheMSBisloadedfirst.The
DAC register loads the data from the shift register when
CS/LD is pulled high. The clock is disabled internally when
CS/LD is high. Note: CLK must be low before CS/LD is
pulled low to avoid an extra internal clock pulse. The input
word must be 16 bits wide. The last two bits are don’t
cares.
Voltage Output
TheLTC1658rail-to-railbufferedoutputcansourceorsink
5mA over the entire operating temperature range while
pulling to within 400mV of the positive supply voltage or
ground. The output swings to within a few millivolts of ei-
ther supply rail when unloaded and has an equivalent out-
putresistanceof40Ω,at5VVCC,whendrivingaloadtothe
rails. The output can drive 1000pF without going into os-
cillation.
The buffered output of the 16-bit shift register is available
on the DOUT pin which swings from GND to VCC.
Multiple LTC1658s may be daisy-chained together by
connecting the DOUT pin to the DIN pin of the next chip
while the clock and CS/LD signals remain common to all
chips in the daisy chain. The serial data is clocked to all of
The output swings from 0V to the voltage at the REF pin,
i.e., there is a gain of 1 from REF to VOUT. Please note, if
REFistiedtoVCC theoutputcanonlyswingto(VCC –VOS).
See Applications Information.
7
LINEAR_DIMENSIONS [ Linear Dimensions ]
