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LTC1658CS8PBF 参数 Datasheet PDF下载

LTC1658CS8PBF图片预览
型号: LTC1658CS8PBF
PDF下载: 下载PDF文件 查看货源
内容描述: 14位轨至轨微DAC ,采用MSOP [14-Bit Rail-to-Rail Micropower DAC in MSOP]
分类和应用:
文件页数/大小: 12 页 / 242 K
品牌: LINEAR_DIMENSIONS [ Linear Dimensions ]
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LTC1658  
ELECTRICAL CHARACTERISTICS  
VCC = 2.7V to 5.5V, VOUT unloaded, REF VCC, TA = TMIN to TMAX, unless otherwise noted.  
SYMBOL PARAMETER  
Output Impedance to GND  
Output Line Regulation  
AC Performance  
Voltage Output Slew Rate  
CONDITIONS  
MIN  
TYP  
MAX  
200  
1.5  
UNITS  
Input Code = 0  
70  
Input Code = 16383, V = 2.7V to 5.5V, REF = 2.5V  
mV/V  
CC  
0.35  
1.0  
12  
V/µs  
µs  
Voltage Output Settling Time (Note 3) to ±0.5LSB  
Digital Feedthrough  
0.3  
nV• s  
Reference Input  
R
REF Input Resistance  
REF Input Range  
30  
0
60  
kΩ  
IN  
V
(Notes 5, 6)  
V
V
REF  
CC  
Digital I/O  
V
V
V
V
V
V
V
V
Digital Input High Voltage  
Digital Input Low Voltage  
Digital Output High Voltage  
Digital Output Low Voltage  
Digital Input High Voltage  
Digital Input Low Voltage  
Digital Output High Voltage  
Digital Output Low Voltage  
Digital Input Leakage  
V
V
V
V
V
V
V
V
V
= 5V  
2.4  
V
V
IH  
IL  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
IN  
= 5V  
0.8  
0.4  
0.6  
= 5V, I  
= 5V, I  
= 3V  
= 1mA, D  
Only  
V
V
– 0.7  
CC  
V
OH  
OL  
IH  
OUT  
OUT  
OUT  
= 1mA, D  
Only  
V
OUT  
OUT  
2.0  
V
= 3V  
V
IL  
= 3V, I  
= 3V, I  
= 1mA, D  
Only  
Only  
– 0.7  
CC  
V
OH  
OL  
LEAK  
OUT  
= 1mA, D  
0.4  
±10  
10  
V
OUT  
OUT  
I
= GND to V  
µA  
pF  
CC  
C
Digital Input Capacitance  
(Note 6)  
IN  
Switching (V = 4.5V to 5.5V)  
CC  
t
t
t
t
t
t
t
t
t
D
D
Valid to CLK Setup  
Valid to CLK Hold  
40  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
1
2
3
4
5
6
7
8
9
IN  
IN  
CLK High Time  
(Note 6)  
(Note 6)  
(Note 6)  
(Note 6)  
(Note 6)  
40  
40  
50  
40  
20  
5
CLK Low Time  
CS/LD Pulse Width  
LSB CLK to CS/LD  
CS/LD Low to CLK  
D
OUT  
Output Delay  
C
= 15pF  
LOAD  
100  
CLK Low to CS/LD Low  
(Note 6)  
20  
Switching (V = 2.7V to 5.5V)  
CC  
t
t
t
t
t
t
t
t
t
D
D
Valid to CLK Setup  
Valid to CLK Hold  
60  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
1
2
3
4
5
6
7
8
9
IN  
IN  
CLK High Time  
(Note 6)  
(Note 6)  
(Note 6)  
(Note 6)  
(Note 6)  
60  
60  
80  
60  
30  
10  
30  
CLK Low Time  
CS/LD Pulse Width  
LSB CLK to CS/LD  
CS/LD Low to CLK  
D
OUT  
Output Delay  
C
= 15pF  
LOAD  
150  
CLK Low to CS/LD Low  
(Note 6)  
3
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