LT8697
pin FuncTions
V (Pins 5, 6): The V pins supply current to the LT8697
USB5V (Pin 20): The LT8697 regulates the USB5V pin to
5V. For cable drop compensation, the USB5V pin input
current is proportional to the sensed output current. The
USB5V ESD cell clamps to 9V. To allow the LT8697 output
IN
IN
internal circuitry and to the internal topside power switch.
These pins must be tied together and be locally bypassed.
Place the positive terminal of the input capacitor as close
as possible to the V pins, and the negative terminal as
to survive a short to 30V, the 10k R
resistor must be
IN
CDC
close as possible to the PGND pins.
in place between the USB5V pin and the output to limit
the current into this pin.
PGND (Pins 7, 8): Power Switch Ground. These pins are
the return path of the internal bottom side power switch
and must be tied together. Place the negative terminal of
the input capacitor as close as possible to the PGND pins.
ISP(Pin21):CurrentSense(+)Pin.Thisisthenon-inverting
input to the current sense amplifier.
ISN (Pin 22): Current Sense (–) Pin. This is the inverting
input to the current sense amplifier.
NC (Pins 9-12): No Connect. These pins are floating and
are not connected to the LT8697. Tie these pins to the
same copper as the exposed pad. See Figure 8.
RCBL (Pin 2ꢀ): Cable Drop Compensation Program Pin.
A resistor R tied from RCBL to ground programs cable
CBL
SW (Pins 1ꢀ, 14, 15): The SW pins are the outputs of the
internal power switches. Tie these pins together and con-
nect them to the inductor and boost capacitor. This node
should be kept small on the PCB for good performance.
drop compensation by setting the USB5V input current.
RCBL can source 1mA. Excessive capacitive loading on
RCBL can degrade load transient response. Isolate load
capacitance on this pin by tying a 100k resistor between
RCBL and the capacitive load. The RCBL load monitor
output is valid when the LT8697 is enabled, otherwise the
output is zero. Float RCBL if neither the current monitor
nor the cable drop compensation feature is desired.
BSꢂ (Pin 16): This pin is used to provide a drive voltage,
higher than the input voltage, to the topside power switch.
Place a 0.1µF boost capacitor between this pin and SW as
close as possible to the LT8697 IC.
ICꢂRL (PIN 24): Current Adjustment Pin. ICTRL adjusts
INꢂV (Pin 17): Internal 3.4V Regulator Bypass Pin. The
CC
the maximum V – V drop before the LT8697 limits
ISP
ISN
internal power drivers and control circuits are powered
the output current. Connect directly to INTV or float for
CC
from this voltage. The INTV maximum output current
CC
a full scale V – V threshold of 48mV or apply values
ISP
ISN
is 20mA. INTV current will be supplied from SYS if
CC
between ground and 1V to modulate the output current
V
SYS
> 3.1V, otherwise current will be drawn from V .
IN
limit. There is an internal 2µA pull-up current on this pin.
Decouple this pin to power ground with at least a 1µF low
Float or tie to INTV when unused.
CC
ESR ceramic capacitor. Do not load the INTV pin with
CC
external circuitry.
GND (Exposed Pad Pin 25): Ground. The exposed pad
must be connected to the negative terminal of the input
capacitor and soldered to the PCB for proper operation
and in order to lower the thermal resistance.
SYS (Pin 18): The internal regulator will draw current
from SYS instead of V when SYS is tied to a voltage
IN
higher than 3.3V. The SYS pin must be tied to the side of
the inductor opposite the SW pin and must be bypassed
by the output capacitor. SYS is also the secondary input
to the error amp and regulates to a maximum of 5.8V.
PG (Pin 19): The PG pin is the open-drain output of an
internal window comparator. PG remains low until the
USB5V pin is within 9% of the final regulation voltage
and there are no fault conditions. The PG transition delay
is approximately 40µs. PG is valid when V is above 3.4V
IN
regardless of the EN/UV state.
8697p
9
For more information www.linear.com/LT8697
LINEAR_DIMENSIONS [ Linear Dimensions ]
