LTC2960
PIN FUNCTIONS
ADJ: Reset Threshold Adjustment Input. Tie to resistive
divider to configure desired reset threshold.
OUT: (LTC2960-1/LTC2960-3) Pulls low when monitored
+
voltage falls below the IN threshold. Released when
+
the IN voltage rises above its threshold by 5%. For the
DV : (LTC2960-3/LTC2960-4) Logic Supply Input. Used
CC
LTC2960-3, OUT is driven by DV when logic high. OUT
CC
for setting the logic swing of the RST and OUT outputs.
is open drain if DV is grounded. Leave open if unused.
CC
Useful for interfacing with logic voltages different from
(LTC2960-2/LTC2960-4)OUTpullslowwhenthemonitored
V . Bypass DV with 0.1μF to GND. Grounding DV
CC
CC
CC
–
voltage rises above the IN threshold. Released when
allows OUT and RST to act as open drain outputs.
–
monitoredvoltagefallsbelowIN thresholdby5%. Forthe
ExposedPad(DFNOnly):Exposedpadmaybeleftfloating
or connected to device ground.
LTC2960-4, OUT is driven to DV for a logic high. OUT
CC
is open drain if DV is grounded. Leave open if unused.
CC
GND: Device ground.
RST:ResetOutput. Pullslowwhenmonitoredvoltagefalls
below the reset (ADJ) threshold. RST is released after
monitored voltage exceeds the reset threshold plus 2.5%
hysteresis and after reset timeout period has expired. For
–
–
IN : (LTC2960-2/LTC2960-4) IN Threshold Adjustment
Input. Tie to resistive divider to configure required thresh-
old. Tie to GND if unused.
the LTC2960-3/LTC2960-4, RST is driven to DV for a
CC
+
+
IN : (LTC2960-1/LTC2960-3) IN Threshold Adjustment
Input. Tie to resistive divider to configure required thresh-
old. Tie to GND if unused.
logic high. RST is open drain if DV is grounded. Leave
CC
open if unused.
RT: (LTC2960-1/LTC2960-2) Reset Timeout Period Se-
MR: Manual Reset Input. Attach a push-button switch or
logic signal between this input and ground. A logic low
on this input pulls RST low. When the MR input returns to
logic high, RST returns high after a reset timeout period
has expired. Leave open if unused.
lection Input. Tie to GND for 15ms delay. Tie to V for
CC
200ms delay.
V : Power Supply Input. When V falls below the falling
CC
CC
UVLO threshold, the outputs are pulled low. If V falls
CC
below 1.2V the logic state of the outputs cannot be guar-
anteed. Bypass V with 0.1μF to GND. Use appropriate
CC
voltage rating for bypass capacitor.
2960f
6
Linear Systems [ Linear Systems ]
