LTC2960
APPLICATIONS INFORMATION
provideeffectivepull-downwithoutexcessivelyloadingthe
pull-up circuitry. A 100k resistor from output to ground is
satisfactoryformostapplications.Whenthestatusoutputs
are high, power is dissipated in the pull-down resistors.
and MR is a solution to this issue. The MR input can be
pulled to 36V maximum and will not affect the internal
circuitry. Input MR is often pulled down through the use
of a pushbutton switch.
If V falls below the falling UVLO threshold, the outputs
CC
SELECTING THE RESET TIMEOUT PERIOD
are pulled to ground. The outputs are guaranteed to stay
lowforV ≥1.2Vregardlessoftheoutputlogicconfigura-
CC
UsetheRTinput(LTC2960-1/LTC2960-2)toselectbetween
two fixed reset timeout periods. Connect RT to ground for
tion. When V < 1.2V, the active pull-up output behaves
CC
similarly to an open-drain output with a pull-up resistor.
a 15ms timeout. Connect RT to V for a 200ms timeout.
CC
The reset timeout period occurs after the ADJ input is
drivenabovethresholdandtheMRinputtransitionsabove
its logic threshold. After the reset timeout period, the RST
output is allowed to pull up to a high state as shown in
LTC2960-3
DV
CC
1.6V TO 5.5V
Figure 5. The RT input is replaced by the DV input in
CC
0.4V
OUT
+
–
the LTC2960-3/LTC2960-4 options and the reset timeout
period defaults to 200ms.
+
IN
ADJ
(a). PUSH-PULL CONFIGURATION
LTC2960-3
15ms
RST, RT = GND
DV
CC
200ms
6.3V MAX
RST, RT = V
CC
2960 F05
0.4V
OUT
+
–
Figure 5. Selectable Reset Timeout Period
+
IN
EXTERNAL HYSTERESIS
+
+
2960 F04
The LTC2960 IN comparator hysteresis is 20mV (V
),
HYS
(b). OPEN-DRAIN CONFIGURATION
or 5% referred to V . Certain applications require more
TH
Figure 4. LTC2960-3 (LTC2960-4) RST and OUT Outputs are
than the built-in native hysteresis. The application sche-
matic in Figure 6 adds one additional resistor (R6) to a
typical attenuator network. The procedure below is used
to determine a value for R6 to provide an increase over
the native hystereis. In this example, it is desired to double
the native hysteresis from 300mV to 600mV and achieve
a falling threshold of 6V.
Configurable as Push-Pull or Open-Drain
MANUAL RESET INPUT
When ADJ is above its reset threshold and the manual
reset input (MR) is pulled low, the RST output is forced
low. RSTremainslowfortheselectedresettimeoutperiod
after the manual reset input is released and pulled high.
The manual reset input is pulled up internally through a
1μA current source to an internal bias voltage (see Elec-
trical Characteristics). If external leakage currents have
the ability to pull down the manual reset input below its
Before including R6, the rising threshold (V ) is 6.293V
R
while the falling threshold (V ) is 5.993V. The hysteresis
F
referred to V is calculated from:
A
R4
R5
⎛
⎞
VHYST VA) = V
1+
=20mV•15 = 300mV
⎜
⎝
⎟
⎠
(
PHYS
logic threshold, a pull-up resistor placed between V
CC
2960f
10
Linear Systems [ Linear Systems ]
