Data Sheet
Austin SuperlynxTM II SIP Non-isolated Power Modules:
March 31, 2008
2.4 – 5.5Vdc input; 0.75Vdc to 3.3Vdc Output; 16A output current
Test Configurations
Design Considerations
Input Filtering
CURRENT PROBE
TO OSCILLOSCOPE
The Austin SuperLynxTM SIP module should be
connected to a low-impedance source. A highly inductive
LTEST
VIN(+)
1μH
source can affect the stability of the module. An input
capacitance must be placed directly adjacent to the input
pin of the module, to minimize input ripple voltage and
ensure module stability.
CIN
CS 1000μF
Electrolytic
2x100μF
Tantalum
E.S.R.<0.1Ω
@ 20°C 100kHz
To minimize input voltage ripple, low-ESR polymer and
COM
ceramic capacitors are recommended at the input of the
module. Figure 26 shows the input ripple voltage (mVp-
p) for various outputs with 1x150 µF polymer capacitors
(Panasonic p/n: EEFUE0J151R, Sanyo p/n: 6TPE150M)
in parallel with 1 x 47 µF ceramic capacitor (Panasonic
p/n: ECJ-5YB0J476M, Taiyo- Yuden p/n:
NOTE: Measure input reflected ripple current with a simulated
source inductance (LTEST) of 1μH. Capacitor CS offsets
possible battery impedance. Measure current as shown
above.
Figure 23. Input Reflected Ripple Current Test Setup.
CEJMK432BJ476MMT) at full load. Figure 27 shows the
input ripple with 2x150 µF polymer capacitors in parallel
with 2 x 47 µF ceramic capacitor at full load.
COPPER STRIP
VO(+)
COM
RESISTIVE
LOAD
300
250
200
150
1uF
.
10uF
SCOPE
GROUND PLANE
NOTE: All voltage measurements to be taken at the module
terminals, as shown above. If sockets are used then
Kelvin connections are required at the module terminals
to avoid measurement errors due to socket contact
resistance.
100
3.3Vin
50
5Vin
Figure 24. Output Ripple and Noise Test Setup.
0
0.5
1
1.5
2
2.5
3
3.5
Rdistribution Rcontact
Rcontact Rdistribution
Output Voltage (Vdc)
VIN(+)
VO
Figure 26. Input ripple voltage for various output
with 1x150 µF polymer and 1x47 µF ceramic
capacitors at the input (full load).
RLOAD
VO
VIN
200
180
160
140
120
100
80
Rdistribution Rcontact
Rcontact Rdistribution
COM
COM
NOTE: All voltage measurements to be taken at the module
terminals, as shown above. If sockets are used then
Kelvin connections are required at the module terminals
to avoid measurement errors due to socket contact
resistance.
60
3.3Vin
Figure 25. Output Voltage and Efficiency Test Setup.
40
5Vin
20
VO. IO
0
Efficiency
=
x
100 %
η
0.5
1
1.5
2
2.5
3
3.5
VIN. IIN
Output Voltage (Vdc)
Figure 27. Input ripple voltage for various output
with 2x150 µF polymer and 2x47 µF ceramic
capacitors at the input (full load).
LINEAGE POWER
10
LINEAGEPOWER [ LINEAGE POWER CORPORATION ]
