LM170E01
Liquid Crystal Display
Product Specification
3-3. Signal Timing Specifications
This is the signal timing required at the input of the LVDS Transmitter. All of the interface signal timing
should be satisfied with the following specifications for it’s proper operation.
Table 6. Timing table
Max.
Parameter
Period
Symbol
tCLK
Min.
14.71
45
672
8
Unit
ns
Notes
Typ.
18.52
54
22.22
Dclk
Frequency
Period
fCLK
68
MHz
tHP
844
56
1022
Hsync
Horizontal period
should be even
tCLK
Width
tWH
-
Period
tVP
tWV
fV
1032
2
1066
3
1536
tHP
Vsync
Width
24
Hz
Frequency
Horizontal Valid
Horizontal Back Porch
Horizontal Front Porch
50
640
16
8
60
76
tHV
tHBP
tHFP
-
640
124
24
640
-
tCLK
-
-
-
-
-
1024
124
-
Vertical Valid
DE
tVV
tVBP
tVFP
-
1024
5
1024
38
Vertical Back Porch
Vertical Front Porch
(Data
Enable)
tHP
1
1
-
-
-
DE setup time
DE hold time
tSI
tHI
tSD
tHD
4
4
4
4
-
-
-
-
-
-
-
-
ns
ns
For Dclk
For Dclk
Data setup time
Data hold time
Data
Notes : 1. DE Only mode operation
2. tHFP + tWH + tHBP < (1/2) tHV
3. tVFP + tWV + tVBP < tH_max / tv_min
4. tHFP, tWH and tHBP should be any times of a character number (8).
5. No variation of the total number of Hsync and DE in a frame is required for normal operation.
6. No variation of the total number of clock in a Hsync period for tVBP is required for normal operation.
12 / 28
Ver 1.0
Mar. 28, 2005
LG [ LG SEMICON CO.,LTD. ]
